Embedding Technologies Advanced Functionalities for Printed Circuit Boards

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1 Embedding Technologies Advanced Functionalities for Printed Circuit Boards Klaus-Dieter Lang Fraunhofer IZM ()

2 Systemintegration auf organischen Substraten Signal/Power Umverdrahtung -Feinstleitertechnik -ungehäuste IC s 2D System Integration -Ultra-Feinstleitertechnik -Modultechnologien 3D System Integration Multifunktionale, Formfaktor optimierte Integration Memory ASIC CPU DSP -eingebettete IC s -optische Verbindungstechnik -Polymersensoren -Extrem dünne systeme -autonome Systeme -Dünnfilmverdrahtung -reaktive Kontakte -Selbstjustage -Energiemanagement H. Reichl, R. Aschenbrenner, H. Pötter, K.-D. Lang (Fraunhofer IZM, Berlin)

3 Printed Circuit Board Embedding Technology Chip in Polymer

4 What Means Embedding? Conventional SMD, Wirebond, Flip Chip Embedding components are located on the surface of a substrate components are inside a substrate

5 Chip Embedding Technologies Approaches Imbera - Integrated Module Board Casio - Embedded WLP GE Chips First Build-Up Fraunhofer IZM - Chip in Polymer

6 Component Embedding Passives Actives Resistors Capacitors Inductors Thick Film polymer printing Thin Film sputtering electroless deposition laminate laminate polymer printing etched copper electroplating printing ferromagnetic s embedded bare dies embedded packages embedding of discrete components

7 Interconnect Evolution First level chip interconnection technologies inside a package: chip & wire flip chip chip embedding established since 40 years smallest in 2D smallest in 3D

8 Chip Embedding Technology via to substrate via to chip chip RCC core substrate adhesive First patent Philips 1968 Chip in Polymer patent IZM 1999 Features of Chip Embedding Technology chip embedding by PCB technology direct Cu contact to chip, no wires, no solder joints improved electrical performance and reliability thin planar packaging enables 3D stacking

9 Where to Use Embedding? Complex Systems Packages / System in Packages / Modules many different components high risk in yield one / few components

10 Packages with Embedded Components Chip embedding technology enables the manufacturing of thin planar packages and stacked SiPs SiP with sequential stack of tested build-up layers packages flat packages / SiPs package on package chip + passive package stack flat single chip package

11 Process Flow Chip Embedding Technologies face up chip attach face down embedding by lamination via drilling Cu plating and structuring electrical and thermal backside contact better fine pitch capability

12 Technology Challenges - Alignment Cu structuring Cu structure to microvia via plating pad preparation lmicrovia to chip pad 60 µm Via, 150 µm pitch chip to core substrate

13 Technology Challenges - Chip Supply and Preparation purchasing of complete wafers is still an issue Cu bumps or electroless NiPd bumps are necessary small pitches require an additional redistribution layer (RDL) Solutions for prototypes and small volumes Au stud bumps single chip thinning embedding of flip chips with adhesive bonding

14 Technnology Challenges for Substrates Integration of optics integration of waveguides and coupling structures Further increase of circuit density new conductor formation technologies High frequencies integrated antennas Shape-conforming to any surface transition flexible stretchable

15 New Substrate Technology Line at Fraunhofer IZM substrate and embedding technologies on 18"x24" (610mm x 456mm) lamination press, 4 stages, oil heated 2-spindle drilling machine Microbeam laser drilling machine Laser Direct Imaging Develop, Etch & Strip horizontal line automatic via filling and plating tool manual bench for surface finish high-speed SMD and bare die placer high accuracy optical inspection Flying probe in-circuit tester Laser Drilling Laser Direct Imaging

16 New Substrate Technology Line at Fraunhofer IZM Etching / Stripping Surface Finish Electroplating

17 QFN Layout QFN Package Test Vehicle size 10x10 mm² thickness.140 µm 84 I/Os, 400 µm pitch chip size 5x5 mm chip pitch 100 µm test vehicle for advanced developments new materials alternative interconnects defect mechanism study realisation in lab environment panel size 350x250 mm² 600 QFN per panel version A version B

18 QFN Packages Realisation first panels realised with 30 µm vias total QFN thickness 150 µm QFN with embedded chip first reliability tests moisture sensitivity test C/85% rh / reflows 260 C test passed, no delamination acoustic image after MSL 1 test

19 Dual-Chip SIP PoP memory analog chip baseband chip top RCC 2 top RCC 1 top chip adhesive adhesive bottom chip bottom RCC 1 bottom RCC 2 System in Package BGA Module 2 embedded chips 5 Cu routing layers stacked micro vias total thickness 450 µm JEDEC Level 2A passed 1000 cycles -55 / C passed 1000 h 85 C / 85 % r. h. passed cross-section of dual chip SiP cross-section of complete SiP x-ray image

20 Application - 77 GHz Automotive Rader System Status: Embedded device achieved excellent performance at 77 GHz, superior to coventional inter- connection technologies. Cost estimations show a 30 % cost reduction. images of embedded RF chip KF. Becker, A. Ostmann, T. Braun, L. Böttcher, M. Koch, R. Kahle (Fraunhofer IZM)

21 Embedded Pacemaker Module realisation of a cardiac pacemaker module with embedded microcontroller assembly of SMD components on top µ-controller embedded in PCB microcontroller embedded in a PCB

22 Concepts for Power Packages and Modules single chip packages for MOSFETs and IGBTs MOSFET MOSFET module with power and logic R logic IC C IGBT IGBT IGBT logic IC EU Project HERMES EU Project SmartPM

23 Infineon Next Generation Package Strategic cooperation with Infineon on embedded component packages Development and realisation of different power package concepts: Single Die Power MOSFET package Multiple Die SiPs combining logic and power ICs (DRMOS) Integrated power supply for processors and graphic controllers Megtaka Different challenges: Combination of required thick Cu metallisation for power with fine pitch requirement of logic Embedded chips and multiple build up layers Die bondung with high thermal and electrical conductivity Single Die NGP Megtaka Chip DRMOS Lars Böttcher, Stefan Karaszkiewicz, David Schütze, Rainer Patzelt, Dept.: SIIT

24 Die derzeit entscheidende Frage für die Zukunft der Embedding-Technologien in der elektronischen Baugruppe ist: Wer übernimmt die Produktverantwortung in der Wertschöpfungskette, die Leiterplattenindustrie oder die Systemhersteller?

25 SMT-Kongresstag Embedding-Technologien und ihre Wertschöpfungskette bei elektronischen Baugruppen Vormittag Embedding-Technologien als Steigerung der Wertschöpfung in der Leiterplatte 1. J. Stahr (AT&S): Embedding-Technologien ein Überblick zu Entwicklungsstand, Märkten und Anwendungen 2. A. Ostmann (Fraunhofer IZM): Zukünftige Entwicklungen zum Embedding in Polymersubstraten 3. L. Pietrzak (Koenen): Hochwertige Schablonentechnik für die Integration höhenverteilter Komponenten in die Leiterplatte 4. T. Gottwald (Schweizer Elektronik): Chip-Einbettung in Multilayer Substrate 5. H. Kostner (Datacon): Dünnchip-Montage für Embedding 6. J. Kostelnik (Würth): Die funktionelle Integration von aktiven und passiven Komponenten in die Leiterplatte im industriellen Umfeld Nachmittag Anwenderanforderungen und Erfahrungen zum Einsatz von Embedding-Verfahren 1. T. Hoffmann, B. Schuch (Continental): Anwendung von Embedding-Technologien aus Sicht eines Herstellers von Automobilelektronik 2. O. Hellmund (Infineon): Einbett-Technologie in der Power-Elektronik 3. F. Betschon (Vario-Optics): Integration planarer Polymerwellenleiter 4. M. Sachs (db-electronic): Heatsinkleiterplatten für Power- LED-Anwendungen 5. M. Gossler (MSE): Assembly und Packaging von Elektronikmodulen für medizinische Implantate ein Überblick 6. M. Riester (Maris Techcon): Anwendungstrends und Marktfelder der Einbetttechnologien im Vergleich zur Standard HDI-Technik

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