Silizium 3D Integration

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1 Silizium 3D Integration All Silicon System Integration All Silicon System Integration Dresden ASSID Prof. Dr.-Ing. Dr.-Ing. E. h. Herbert Reichl

2 Interconnects today: 2010 WB 25µm FC CSP BGA Interposer 100 µm HDI 130 µm 0.65mm PCB

3 Trend Interconnects: 2015 Silicon Interposer WB 25 /20µm FC CSP BGA SiP Interposer 100/ 70 µm HDI µm mm PCB

4 Chip Stack Trend Interconnects: 2015 Rewiring Layer Silicon Interposer SiP Silicon 3D Integration All Silicon System Integration Through Silicon Via - TSV Interconnects to PCB Interposer

5 Silicon interposer Silicon interposer as Device Carrier Substrate between Devices and Package/Board for high IO Count high Interconnect Density Silicon Interposer Compute µp Die Metal RDL Layers Multi Metal Layers RDL Organic Substrate Substrate Memory Die(s) Metal RDL Layers 1or 2-8 dies Rewiring Memory Die(s) Metal RDL Layers TSV Silicon

6 Silizium 3D Integration Driving Forces for Silicon 3D Systemintegration Form Factor & Miniaturization Reduced volume and weight Reduced footprint Performance Improved integration density Reduced interconnect length Improved transmission speed Reduced power consumption Heterogeneous Integration & Functionality Integration of devices from different technologies Sensors, MEMS, AD SP, Transceiver Reliability Aspects Cost Reduction

7 3D All Silicon Integration - Silicon Interposer Trends 2010 / µm 1.6 µm RDL Cu line space/thickness: 15 µm / 5µm 2µm / <2µm interposer Joiner 70 µm 15 µm BGA ball via density: 2500 via/mm² > via/mm² 40 µm 3.3 µm Theoretical Vias pro mm², practical >40 000/mm²

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9 System in Package (>2010) TSV Number of die accommodated in a package: 10 pcs Maximum number of die stacked: 8 pcs Mold resin thickness on top of die: 0.10 mm 0.025mm 1.0 mm Silicon Interposer 4 layer RDL, 10µm line/space Substrate thickness: 0.16mm Ball pitch: 0. 8 mm Ball diameter: 0.4 mm Embedded after ITRS, modified by Reichl

10 Evolution of 3D Integration 3D Pkg Chip Stack Analog Flash DRAM DRAM CPU 3D Through Via Chip Stack 3D Flip Chip Package Stack Increasing 3D Integration Zunächst vom Memory Stack getrieben! Wire bonded chip stacked 3D K. Bernstein, New Dimensions in Performance: Emerging 3D Integration Technologies," VMIC 2006

11 Roadmap 3D WL System Integration 3D TCT/TSV 3D Interconnect Complexity WLP w. TSV Controller / Memory Stacks ewlp ewlp 3D Image Sensors Stacked Memory on TSV Interposer ewlp w TMV HDI TSV Interposer Stacked TCI w TSV Hetero Integration 3D Interposer w. Cooling 3D CPUs Functional Layered Stack µegrain Application getrieben! IPD & RDL 08/ Year

12 TSV Roadmap µp Modules Logistic, Security Automotive Source: Yole

13 Smart Presssure Sensor 7 Energy Harvesting MEMS Harvester- ASIC Cap./thin film bat. appr. 4.5 Rim based TPMS Today s product Large size Battery TPMS Sensor and ASIC (Infineon) Volume: 60 cm³ Valve plus TMPS System (Tier1) Volume: appr. 60 cm 3 Technichal Features: Low weight (< 5g), low volume high robustness ( g acceleration) Low power ASIC (IFX) (< 10x ) Miniaturized Tire Pressure Monitoring System Courtesy: Infineon e-cubes

14 Stacked 3D Camera Module FKZ 01M3163A, 01M3163B

15 Stacked 3D Camera Module Glass with Front Side RDL IC1 with Micro Bumps Interposer with TSV and FS/BS RDL IC2 with Micro Bumps SnAg balls PbSn balls glass Sensor interposer provessor cross section of 3D camera stack through the middle of the package FKZ 01M3163A, 01M3163B

16 Maßnahmen zur Unterstützung der Anwendung der Silizium 3D Integration in Deutschland Leistungsfähigkeit der Technologie auf internationalen Niveau demonstrieren Kostengünstige Produktionsmöglichkeiten aufzeigen (300 mm) Flexibilität der Technologie für unterschiedlichste Applikationen nachweisen Vollständige Technologie für Interposer, Die-Assembly und Packaging Durchängiger Prozeßflow - Design/Technologie/Test/Qualitätssicherung Geräte und Technologien der Hersteller-Industrie zugänglich machen Europäischen Forschungs- und Entwicklungsschwerpunkt aufbauen

17 All Silicon System Integration Dresden ASSID Fraunhofer IZM Dresden June 2009

18 All Silicon System Integration Dresden FhG IZM IZM vision: Heterogene Funktionen höchster Dichte in einem Package mit Hilfe der 3D-Silizium Integration.

19 ASSID Mission Provide solutions ready for product integration IZM / ASSID develops leading edge technologies for 3D- WL System-Integration and provide solutions ready for product integration to industrial partners. IZM / ASSID offers capacity and support for equipment and material evaluation to semiconductor industry. IZM / ASSID offers services by using qualified process capacities and demonstrate stable processes on a 300mm TSV process line.

20 ASSID Key Figures & Location Total Clean Room Area: 975* sqm Clean Room Area (class 1000): 710* sqm Laboratory Area (class ): 265* sqm Office Building Area: 620 sqm * according to reconstruction plan 2010 GF ASSID

21 Floorplan: RDL, TSV, Bumping Interposer Technologien

22 TSV-Etcher Basic Process Flow Interposer Via Formation UBM-Pad BS UBM-Pad Cleaner Si Via Etching (RIE) Isolation (CVD,therm.) Barrier (IMP) Barrier-/Seedlayer Deposition Temp Bonding /De-Bonding Support Wafer Bonding Wafer Transfer De-/Temp Bond ECD ECD Via Filling, Cu Cu-CMP RDL, Cu Wafer Thinning Grinder /Plasma BS-Aligner BS Passivation Bonder, Underfill Die to Wafer Assembly Reflow Molding / Balling / Singulation Dielectric Polymer Layer Spray Etcher

23 All Silicon System Integration IZM Topic: 3D WLP (300 mm Process line) with focus on Cu Through Silicon Vias (TSV) TSV formation > Thinning > Handling > WL Assembly > Package Major technical tasks: High density High Aspect Ratio Cu-TSV TSV density: > TSVs /cm² Padless interconnection Multilayer FS/BS RDL line / space <5 µm Integrated passive devices Bumpless device integration

24 TSV Deep Trench Si Etching Etch Depth: 95 µm (Ø 20 µm) AR (aspect ratio): 4.8 : 1 TSV etch rate: 3,1 µm/min Taper angle: 89,5 Open area: ~ 8-10 % TSV holes, AR 4.8 : 1, sample #05, center

25 Silicon Interposer with Cu TSV & RDL Cu TSV (diam. 20 µm; 100 µm depth) 3 TSV/IO Top Metal (IO-FC) Via 3T RDL3 Via 23 Via 12 RDL2 Via B1 RDL1 Top Metal TSV

26 Si Interposer Front side: 4 Layers Cu RDL Min.15µm line / 30 µm space TSV: > TSV/cm² (>44k/interposer) Back side: Cu Pillar (40 µm) Cross section with Cu-TSV Front and backside view of full processed Si Interposer with CuTSV

27 TSV - Interposer with assembled Devices in Package position of the cross section cross section of a fully assembled package with flip chip assembled electronic devices TSV- INTERPOSER CIRCUIT TSV package

28 Terminplan 13. Januar 2009 Förderentscheidung durch das sächsische Kabinett 17. Februar 2009 Beschluss im FhG-Ausschuss über die gemeinsame Förderung durch FhG/Bund und Freistaat Sachsen, Förderantrag an die SAB 29.Okt Nov 2009 ab Okt Nov Januar 2010 Febr. Q2 / 2010 Q4 / 2010 Bewilligung Invest durch Bund und SAB (Land Sachsen) Erwerb der Liegenschaft inkl. spez. 300mm Process Tools Ausschreibungsverfahren für Geräteerweiterung Re-Konfiguration der vorhandenen Reinraumausstattung Reconf/ Upgrade Processtools schrittweise Prozessimplementation Bewilligung BMBF Grundlagenprojekt Process Setup 300 mm - Erster Litho Wafer Sputtering, Electrodeposition, Etching Beginn Lieferung und Installation Neugeräte Prozess/ Equipment Komplettierung ASSID

29 Status 03/ mm Lithography, Cu-ECD and Etch in Operation January, 18th, 2010 First 300 mm wafer ASSID

30 Setup und Aufbau Personal per Wi Mi + Techniker Plan Q2/2010 gesamt 25 Mitarbeiter Projekte Förderung Invest und Sonderfinanzierung (Bund+Freistaat Sachsen) Grundlagenprojekt BMBF Industieprojekte (i.p.) EU Projekte (ENIAC, Catrene) (i.v)

31 Wissenschaftlich technische Zusammenarbeit mit Instituten und Universitäten auf regionaler Ebene 3D Design Mikro-Nano-Analytik Komponentenentwicklung MEMS Integration Cu CVD Barrier/Seed Metallisierung und Waferbonding Assembly Technologien Silicon 3D Technologien Ätzen, Oxidation, Seedlayer Via-Filling, Assembly, Packaging Fraunhofer IIS-EAS Fraunhofer IzfP Fraunhofer IPMS Fraunhofer ENAS TU-Dresden Fraunhofer IZM IZM-München IZM-Berlin

32 All Silicon System Integration Dresden ASSID Contact: Prof. Herbert Reichl Dr. Klaus-Dieter Lang M. Juergen Wolf All rights: