Übung 3: VHDL Darstellungen (Blockdiagramme)

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1 Übung 3: VHDL Darstellungen (Blockdiagramme) Aufgabe 1 Multiplexer in VHDL. (a) Analysieren Sie den VHDL Code und zeichnen Sie den entsprechenden Schaltplan (mit Multiplexer). (b) Beschreiben Sie zwei weiteren Architekturen für die gleiche Funktionalität. Eine mit AND-OR Operatoren und eine mit IF-ELSE Anweisungen. (c) Welche von den 4-Architekturen bevorzugten Sie und warum? -- Multiplexer is a device to select different -- inputs to outputs. we use 3 bits vector to -- describe its I/O ports entity Mux is port( I3: in std_logic_vector(2 downto 0 I2: in std_logic_vector(2 downto 0 I1: in std_logic_vector(2 downto 0 I0: in std_logic_vector(2 downto 0 S: in std_logic_vector(1 downto 0 O: out std_logic_vector(2 downto 0) end Mux; architecture behv1 of Mux is process(i3,i2,i1,i0,s) -- use case statement case S is when "00" => O <= I0; when "01" => O <= I1; when "10" => O <= I2; when others => O <= I3; end case; end behv1; architecture behv2 of Mux is -- use when.. else statement O <= I0 when S="00" else I1 when S="01" else I2 when S="10" else I3 ; end behv2; - Quelle: : mux.vhd Seite 1/6

2 Aufgabe 2 Flussdiagramm Darstellung. (a) Analysieren Sie den unteren Code und zeichnen Sie das entsprechende Flussdiagramm. (b) Untersuchen und erklären Sie die Funktion von der GENERIC Anweisung. -- n-bit Comparator use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity Comparator is generic(n: natural :=2 port( A: in std_logic_vector(n-1 downto 0 B: in std_logic_vector(n-1 downto 0 less: out std_logic; equal: out std_logic; greater: out std_logic end Comparator; architecture behv of Comparator is process(a,b) if (A<B) then less <= '1'; equal <= '0'; greater <= '0'; elsif (A=B) then less <= '0'; equal <= '1'; greater <= '0'; else less <= '0'; equal <= '0'; greater <= '1'; end if; end behv; Quelle: : comparator.vhd Seite 2/6

3 Aufgabe 3 Hardware-Register Darstellung. (a) Analysieren Sie den VHDL Code und zeichnen Sie einen Blockdiagramm, das die Funktionalität und Aufbau der IO-Signale erklärt. (b) Untersuchen Sie das PACKAGE IEEE_STD_LOGIC_UNSIGNED in ModelSim, und bestimmen Sie, welchen Datentypen die Operation + für unsigned Vektoren unterstützt. Hinweis: Sie können das PACKAGE im ModelSim Workspace Unterfenster finden: ModelSim>Workspace>Library>IEEE>std_logic_unsigned>edit VHDL code for n-bit adder function of adder: -- A plus B to get n-bit sum and 1 bit carry -- we may use generic statement to set the parameter -- n of the adder use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ADDER is generic(n: natural :=2 port( A: in std_logic_vector(n-1 downto 0 B: in std_logic_vector(n-1 downto 0 carry: out std_logic; sum: out std_logic_vector(n-1 downto 0) end ADDER; architecture behv of ADDER is -- define a temparary signal to store the result signal result: std_logic_vector(n downto 0 -- the 3rd bit should be carry result <= ('0' & A)+('0' & B sum <= result(n-1 downto 0 carry <= result(n end behv; Quelle: : adder.vhd Seite 3/6

4 Aufgabe 4 Testbench Anweisungen. (a) Analysieren Sie den VHDL Code und zeichnen Sie den entsprechenden Schaltplan (mit Multiplexer). (b) Schreiben Sie den VHDL Code für ein Testbench, das die Funktionalität diese ALU überprüft. Benutzen Sie dafür die Anweisungen: WAIT und ASSERT. -- Simple ALU Module ALU stands for arithmatic logic unit. -- It perform multiple operations according to -- the control bits. -- we use 2's complement subraction in this example -- two 2-bit inputs & carry-bit ignored use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity ALU is port( A: in std_logic_vector(1 downto 0 B: in std_logic_vector(1 downto 0 Sel: in std_logic_vector(1 downto 0 Res: out std_logic_vector(1 downto 0) end ALU; architecture behv of ALU is process(a,b,sel) -- use case statement to achieve -- different operations of ALU case Sel is when "00" => Res <= A + B; when "01" => Res <= A + (not B) + 1; when "10" => Res <= A and B; when "11" => Res <= A or B; when others => Res <= "XX"; end case; end behv; - Quelle: : ALU.vhd Seite 4/6

5 Musterlösung Aufgabe 1 (a) Schaltplan für behav1 und behav2 I 0 I 1 I 2 I XX 3 O (b) architecture behv3 of Mux is process(i3,i2,i1,i0,s) -- use if-else statement if (S="00") then O <= I0; elsif (S="01") then O <= I1; elsif (S="10") then O <= I2; else O <= I3; end if; end behv3; S 2 architecture behv4 of Mux is -- use AND-OR statements O(2) <= ( I0(2) AND NOT(S(1)) AND NOT(S(0)) ) OR ( I1(2) AND NOT(S(1)) AND (S(0)) ) OR ( I2(2) AND (S(1)) AND NOT(S(0)) ) OR ( I1(2) AND (S(1)) AND (S(0)) -- (und weiter aber nicht praktisch ) end behv4; (c) Preferred architecture: behav1 with case statement. Two reasons: - case statement implements logic without priority (adequate for multiplexer - logic implemented inside process (faster for simulation). Aufgabe 2 (a) A<B N A=B Y Y less=1 equal=0 greater=0 less=0 equal=1 greater=0 (b) Generic describes a parameter that can be configured (assume different values) for different instantiations of the same block. E.g.: compare signals with different sizes (vector length). N less=0 equal=0 greater=1 Seite 5/6

6 Aufgabe 3 (a) The function of this VHDL code is: - calculate the sum of 2 vectors and generate a carry bit. - the sum is executed with sign-extension, which makes conversion from unsigned to 2- complement notation. 0 & A : 0 A(1) A(0) 0 & B : 0 B(1) B(0) result: r(2) r(1) r(0) A(0) + B(0) A(1) + B(1) + Überlauf(0) Überlauf(1) (b) Data types allowed for + operation in std_logic_unsigned package : Aufgabe 4 (a) 00 A 01 B Res XX XX Sel 2 (b) In order to test your testbench code, you can simulate it in Modelsim. But before you start writing your testbench code, let us think about which scenarios (combinations of inputs) you need to test. This combination of test scenarios is what we call a testplan. Testplan Scenario Mode Input Values Expected Output Values 1 Sum Sel= 00 A + B A : all possible values (4 for 2bit vector) What happens with B : all possible values (4 for 2bit vector) overflow? 2 Sub 3 And 4 OR 5 XX Seite 6/6