6T SRAM six sigma design with WiCkeD

Transkript

1 WiCkeD User Group Meeting 6T SRAM six sigma design with WiCkeD Thomas Fischer

2 Outline Variations Worst Case Distance Analysis WiCkeD Implementation Design for Yield Summary 2

3 Local Variations! σ Vth A Larger local variations in smaller technologies WMinimum L feature size devices (eg. in SRAM) show larger variations Reduced supply voltages and large threshold voltages (leakage reductions) limit the operating range of SRAM cells 3

4 Sources of local variations Lithography related yield and dopant related yield dominate over defect limited yield for new technologies due to Line Edge Roughness Discrete Dopant Fluctuations (e.g. under gate) Vth shift Gate Active S D Poly σ Vt t ox, el 4 N d WL 4

5 Reading a SRAM cell 1 1 V Slope due to parasitic effects BLB I read T pre T read T SA WL Slope determined by I read BL Fire sense amp t The voltage drop caused by the read current I read must be large enough to be detected by the sense amplifier The voltage divider PG and PD defines the read stability (β-ratio) If the storage node voltage on the BL side rises above the switching level the cell flips destructive read 5

6 Reading a SRAM cell Vout / Vin SNM Vin / Vout The Static Noise Margin SNM defines this read stability The inverter characteristics form the Butterfly Curve The smallest opening of the eye is the SNM 6

7 Writing a SRAM Cell 1 0 V BLB BL WL Write Level t Write a 0 ( 1 can not be written due to read stability) Voltage divider PL and PG define write ability Write Level is the voltage on the side driving the 1 at the moment of the cell flipping 7

8 Simulation of Variations in SRAM Simulation of variations in SRAM cells with classical Monte Carlo is very time consuming A large number of simulations is needed due to the large number of SRAM core cells in embedded systems Monte Carlo simulations for different operating corners (Vdd, Temp,..) is very expensive Faster simulations of the influence of variations is needed to incorporate variations issues into the memory design process Worst Case Distance Simulation 8

9 Worst Case Distance Nominal Point Specification pdf σvth PLBLB σvth PLBLB Performance (e.g. Write Level) σvth PGBLB σvth PGBLB Worst Case Distance 9

10 Wost Case Distance Performance distribution for the two dominant parameters 10

11 Worst Case Distance - Yield For each SRAM performance (e.g. SNM, Write Level) a specification is defined. Find the most likely circuit parameter (eg. Vthx, μ0x) configuration for a failure. Distance between failure and nominal is the Worst Case Distance (WCD). Calculate SRAM failure probability with the WCD (Poisson) 11

12 Worst Case Distance - Yield Yield for different array sizes Yield 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% sigma 97,5% 12

13 Global process corner Local Performance Distribution Global variations from process asymmetry Simulate local variations with the parameters of the global process WL / mv mu mu+sig mu-sig Process dvth(pl) / sigma /(global) sigma -2σ 2σ 13

14 First global, then local Worst die at the process corner Global process Local Variations Only global variations (vthn, tox, xl...) are evaluated at first Based on the worst die parameter set the Worst Case Distance for the local variations (dvth, mobility) are evaluated 14

15 First global, then local Assume global variation of e.g. 2 σ Consider only global parameters (vthn, tox, xl...) (1) Find parameter set for 2 σ Worst Case Point (2) Now consider only local parameters (dvth, mobility) (3) Based on global parameters find Worst Case Distance for a given Specification of a performance (e.g. Write Level, Iread) (4) Find the performance for local variations representing the array size (5) Die taken from a worst case waver (1) (2) (3) (4) (5) Mismatch parameter of a memory array 15

16 Scripts SRAM circuit is small and simple. Simulation file and.def file written manually Model file written semi automatically via PERL First global, then local --> TCL Vdd variations Temp Array size Global variations HCI, NBTI PERL for post processing of simulation data GUI 16

17 Yield and operating conditions Worst Case Yield highvt WL -40 C SNM_w_NA 85C Iread -40C sigma (normalized) Operating conditions change yield detractors Design for all operating conditions Vdd 17

18 Transistor sizing Cell Size Options 1,20E+00 1,00E+00 8,00E-01 6,00E-01 4,00E-01 Cell 1 Cell 2 Cell 3 Cell 4 2,00E-01 0,00E+00 0,8 0,85 0,9 0,95 1 1,05 1,1 1,15 1,2 Vdd Calculate Worst Case Distance for different sizing options. Automatic sizing in WiCkeD is difficult due to 5-6 σ design and tight design rules 18

19 Design space Tradeoff Area <-> Yield: Redundancy (find optimum Redundancy scheme with parametric defect densities from WCD analysis) Larger core cells Circuit design: Design cell more stable. Use special write operations (write boost). Yield WCD vs. Yield 1MBit 100% 90% no Redundancy 10 red. words 80% 70% 60% 50% 40% 30% 20% 10% 0% 3.50E E E E E E+00 WCD read stability Evaluation of yield enhancing scenarios with WiCKeD WCA using Good Dies Per Wafer measure. writeability read current 19

20 Summary Worst Case Analysis for 6T SRAM considering local and global variations has proven to be useful also for large number of devices (5-6 σ) Faster than Monte Carlo Multiple design options can be simulated in short time Design for Yield 20