Eingebettete Taktübertragung auf Speicherbussen

Transkript

1 Eingebettete Taktübertragung auf Speicherbussen Johannes Reichart Workshop Hochgeschwindigkeitsschnittstellen Stuttgart, Unterstützt durch: Qimonda AG, München Institut für Prof. Elektrische Dr.-Ing. und Optische Manfred Nachrichtentechnik Berroth 1

2 Outline Introduction: Overview of DDR DRAM generations Increasing memory bandwidth demands Ghost signaling concept: Conventional transmission scheme Transmission scheme with ghost signaling Circuit concepts: Implementation in Current Mode Logic Simulation results: Channel Model of a typical DDR3 interface Ghost signaling on a DDR3 interface 2

3 Overview of DDR Generations The last 3 DRAM DIMM Standards (JEDEC): DDR(1) SO-DIMM with 200 pins (Data bus width of 64 bits) Maximum data bandwidth of 3.2 Gbyte/s Data I/O-speed up to 400 Mbit/s/pin DDR2 SO-DIMM with 200 pins (Data bus width of 64 bits) Maximum data bandwidth of 6.4 Gbyte/s Data I/O-speed up to 800 Mbit/s/pin DDR3 SO-DIMM with 204 pins (Data bus width of 64 bits) Maximum data bandwidth of 12.8 Gbyte/s Data I/O-speed up to 1.6 Gbit/s/pin Doubling the I/O-speed as cheapest solution for each generation 3

4 Costs of increasing the memory speed Doubling the I/O-clock frequency and its costs: Peak bandwidth demand in Gbyte/s DDR1 4 DIMMs possible Entire data bus in sync High demands on mainboard design DDR4? NG? DDR DDR DDR ? I/O-clock in MHz 4

5 Costs of increasing the memory speed Doubling the I/O-clock frequency and its costs: Peak bandwidth DDR2 demand 2-4 DIMMs in Gbyte/s DDR1 4 DIMMs possible Entire data bus in sync High demands on mainboard design possible Each byte required to be in sync Bytewise training routines necessary DDR4? NG? DDR DDR DDR ? I/O-clock in MHz 5

6 Costs of increasing the memory speed Doubling the I/O-clock frequency and its costs: DDR3 Peak bandwidth demand in Gbyte/s DDR1 4 DIMMs possible Entire data bus in sync High demands on mainboard design DDR2 2-4 DIMMs possible Each byte required to be in sync Bytewise training routines necessary Only one single DIMM supported Bits no longer in sync Bitwise training routines necessary! DDR4? NG? DDR DDR DDR ? I/O-clock in MHz 6

7 Costs of increasing the memory speed Doubling the I/O-clock frequency and its costs: Peak bandwidth demand in Gbyte/s DDR1 4 DIMMs possible Entire data bus in sync High demands on mainboard design DDR2 2-4 DIMMs possible Each byte required to be in sync Bytewise training routines necessary DDR3 Only one single DIMM supported Bits no longer in sync Bitwise training routines necessary! DDR3 Next Generation Memory Still unsolved problems like: Data dependent jitter Cross-talk on data lines NG? DDR4? DDR DDR ? Synchronization of clock and data becoming more and more challenging I/O-clock in MHz 7

8 Outline Introduction: Overview of DDR DRAM generations Increasing memory bandwidth demands Ghost signaling concept: Conventional transmission scheme Transmission scheme with ghost signaling Circuit concepts: Implementation in Current Mode Logic Simulation results: Channel Model of a typical DDR3 interface Ghost signaling on a DDR3 interface 8

9 Ghost signaling concept How to ensure data to clock synchrony: Conventional data transmission scheme (differential signaling) data 1 Common mode of data1 signal (constant) data 2 Common mode of data2 signal (constant) clock 9

10 Ghost signaling concept How to ensure data to clock synchrony: Positive clock transmitted as Common Mode of Data1 Negative clock transmitted as Common Mode of Data2 10

11 Ghost signaling concept Using two common modes as one differential clock signal 11

12 Ghost signaling concept Advantages: Clock skew eliminated Crosstalk and noise effects influence both data and clock in the same manner Clock does not need to be distributed on the DIMM and over the chip Drawbacks: Data and clock have to share the signal swing Many independent clock domains on receiver side 12

13 Outline Introduction: Overview of DDR DRAM generations Increasing memory bandwidth demands Ghost signaling concept: Conventional transmission scheme Transmission scheme with ghost signaling Circuit concepts: Implementation in Current Mode Logic Simulation results: Channel Model of a typical DDR3 interface Ghost signaling on a DDR3 interface 13

14 Circuit concepts (90 nm CMOS) Implementation in Current Mode Logic (CML): Ghost signaling transmitter block Four differential current switches with tail current source 14

15 Circuit concepts (90 nm CMOS) Implementation in Current Mode Logic (CML): Ghost signaling transmitter block Four differential current switches with tail current source On chip termination 15

16 Circuit concepts (90 nm CMOS) Implementation in Current Mode Logic (CML): Ghost signaling transmitter block Four differential current switches with tail current source On chip termination Two current switches for data1 and data2 respectively 16

17 Circuit concepts (90 nm CMOS) Implementation in Current Mode Logic (CML): Ghost signaling transmitter block Four differential current switches with tail current source On chip termination Two current switches for data1 and data2 respectively Two current switches for differential Common Mode modulation 17

18 Circuit concepts (90 nm CMOS) Implementation in Current Mode Logic (CML): Ghost signaling receiver block On chip termination 18

19 Circuit concepts (90 nm CMOS) Implementation in Current Mode Logic (CML): Ghost signaling receiver block On chip termination Simple voltage divider for Common Mode extraction 19

20 Circuit concepts (90 nm CMOS) Implementation in Current Mode Logic (CML): Ghost signaling receiver block On chip termination Simple voltage divider for Common Mode extraction Amplification of data and clock with conventional CML buffers That s it! 20

21 Outline Introduction: Overview of DDR DRAM generations Increasing memory bandwidth demands Ghost signaling concept: Conventional transmission scheme Transmission scheme with ghost signaling Circuit concepts: Implementation in Current Mode Logic Simulation results: Channel Model of a typical DDR3 interface Ghost signaling on a DDR3 interface 21

22 Simulations Channel model based on measurements in a DDR3 memory system: Impulse Response to a unit pulse 22

23 Simulation results 6.67 Gbit/s on a typical DDR3 channel Simulation done with the channel model of the memory interface Output of transmitter block Input to receiver block Amplified data Amplified clock Sampled data after latch 23

24 Summary and Outlook Timing in memory systems becomes more and more challenging Transmission channel as constraint Ghost signaling concept: No clock distribution necessary Simple implementation Simulation on a DDR3 channel: 6.67 Gbit/s possible without equalization Improvements in channel characteristics very welcome 24

25 Thank you uestions? 25