Application-specific processor for MIMO-OFDM software-defined radio
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1 Research Collection Doctoral Thesis Application-specific processor for MIMO-OFDM software-defined radio Author(s): Eberli, Stefan Publication Date: 2009 Permanent Link: Rights / License: In Copyright - Non-Commercial Use Permitted This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library
2 Diss. ETH No Application-Specific Processor for MIMO-OFDM Software-Defined Radio A dissertation submitted to ETH ZURICH for the degree of Doctor of Sciences presented by STEFAN EBERLI Dipl. El.-Ing. ETH born citizen of Zürich (ZH) and Hüttwilen (TG) accepted on the recommendation of Prof. Dr. W. Fichtner, examiner Prof. Dr. H. Meyr, co-examiner 2009
3 Abstract Software-defined radios (SDRs) present a promising approach to face the demands of today s fast evolving environment of wireless communication standards. Ever increasing requirements in terms of performance and flexibility call for programmable, high-performance signal processing platforms. Performance is necessary to cope with the high computational burden inherent to wireless communications. Flexibility is desired to shorten the time-to-market. Unfortunately, performance and flexibility are antagonists and are difficult to combine in one single efficient platform, as one is obtained at the cost of the other. This thesis contributes to the SDR research domain, addressing the implementation of a 2 2 MIMO-OFDM receiver on an SDR platform. Appropriate receiver algorithms are evaluated and the corresponding computational complexity is derived. The use of lowcomplexity algorithms is imperative to spare the limited processing resources of a programmable platform. Three software-programmable architectures are evaluated to find a suitable SDR platform, eventually leading to the selection of a design-time configurable applicationspecific processor as platform. The 2 2 MIMO-OFDM receiver is split into two parts which are mapped onto two application-specific processors, each tailored to the computational needs of the associated digital signal processing kernels. The first processor performs the per-stream MIMO-OFDM processing. The second processor handles the MIMO detection. Finally, the 0.18 µm 1P/6M CMOS technology layout of both fabricated application-specific processors is presented: the silicon area required by the two processors is 7.65 mm 2 and realtime baseband processing is possible on these engines running at a clock frequency of 250 MHz. vii
4 Zusammenfassung Software-definierte Radios (SDRs) stellen einen viel versprechenden Ansatz dar, um sich dem heutigen, sich schnell entwickelnden Umfeld der drahtlosen Kommunikationsstandards rasch anpassen zu können. Ständig steigende Anforderungen, in Leistung und Flexibilität ausgedrückt, beanspruchen programmierbare und leistungsstarke Signalaufbereitungsplattformen. Leistung ist notwendig, um mit dem hohen Rechenaufwand fertig zu werden, der der drahtlosen Kommunikation inheränt ist. Flexibilität ist erwünscht, um die time-to-market zu verkürzen. Leider sind Leistung und Flexibilität Antagonisten und schwierig in einer einzelnen, effizienten und leistungsfähigen Plattform zu kombinieren, da das eine auf Kosten des anderen erreicht wird. Diese Arbeit trägt zum SDR-Forschungsgebiet bei und behandelt die Implementierung eines 2 2 MIMO-OFDM Empfängers auf einer SDR-Plattform. Dazu werden passende Empfängeralgorithmen ausgewertet und der entsprechende Rechenaufwand wird abgeleitet. Der Gebrauch von Algorithmen mit niedrigem Rechenaufwand ist zwingend, um kostbare Rechenressourcen einer programmierbaren Plattform einzusparen. Drei Software-programmierbare Architekturen werden evaluiert, um eine geeignete SDR-Plattform zu finden. Ein konfigurierbarer, anwendungsspezifischer Prozessor wird schliesslich als Plattform ausgewählt. Der 2 2 MIMO-OFDM Empfänger wird dann in zwei Teile, die an zwei solcher anwendungsspezifischen Prozessoren angepasst werden, aufgespalten, wobei die Recheneinheiten der zwei Prozessoren auf die Charakteristiken der Algorithmen massgeschneidert sind. Der erste Prozessor führt die Verarbeitung des MIMO-OFDM Datenstromes durch. Der zweite Prozessor behandelt ix
5 x ZUSAMMENFASSUNG die MIMO-Detektion. Zu guter Letzt wird das 0.18 µm 1P/6M CMOS Layout beider gefertigten Prozessoren vorgestellt: die Siliziumfläche der zwei Prozessoren beträgt zusammen 7.65 mm 2 und die Echtzeitdatenverarbeitung ist bei einer Taktfrequenz von 250 MHz möglich.
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