System Design and Channel Equalization for Evolved EDGE Physical Layer
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1 DISS. ETH NO System Design and Channel Equalization for Evolved EDGE Physical Layer A thesis submitted to attain the degree of DOCTOR OF SCIENCES of ETH ZURICH (Dr. sc. ETH Zurich) presented by STEFAN ALTORFER MSc ETH born on August 21, 1981 citizen of Glarus Nord, Switzerland accepted on the recommendation of Prof. Dr. Qiuting Huang, examiner Prof. Dr. Andreas Burg, co-examiner 2015
2 Abstract Evolved EDGE is an advancement of the cellular communication standard of the second generation (2G) with the goal of achieving higher spectral efficiency, better reliability and higher peak data rates. This progress ensures that 2G systems can continue to serve as a competitive fallback solution in places without 3G or 4G coverage. Furthermore, an enhancement of the GSM/EDGE standard consolidates its position as the most universal cellular solution. This is an important attribute since worldwide network coverage is a key requirement for many applications in the emerging field of machine-to-machine (M2M) communication. The significant increase in spectral efficiency of Evolved EDGE is realized by introducing modulation schemes with up to five bits per symbol. However, the high modulation order in combination with the severe inter-symbol interference inherent to 2G systems makes channel equalization and signal detection extremely complex. Equalizer solutions that can cope with this complexity while being small and power-efficient as required for M2M communication systems are most effectively realized by developing application specific integrated circuits (ASIC). Optimal equalization algorithms like maximum-likelihood sequence estimation can only be implemented for legacy GSM modulation at reasonably low complexity. Equalization of Evolved EDGE signals requires reduced-complexity variants to achieve small and power-efficient designs. In this thesis, several of these algorithms are evaluated and optimized with regard to their suitability for an ASIC implementation. It is shown that reduced-state sequence estimation (RSSE) with only 16 trellis states in combination with minimum-phase channel shortening is sufficient to achieve close-to-optimal performance under vii
3 viii multipath fading as specified for 2G. The implemented channel shortening and RSSE solutions improve hardware efficiency of prior art by a factor 5 and 1.6, respectively. Moreover, a substantial performance gain is achieved by providing soft-values to the channel decoder, and the transmission reliability is improved by employing two receive antennas. A highly optimized hardware architecture that implements these two features is presented, boosting error-rate performance by up to 10 db with hardware efficiency degradation of only a factor 2.5. The feasibility of Evolved EDGE is demonstrated by presenting the first-ever baseband transceiver ASIC with a core area of 6 mm 2 in 130 nm CMOS. An integration of the ASIC into a complete physical layer (PHY) system allows assessing the sensitivity and interference performance of the whole processing chain, including RF transceiver. The measured sensitivity performance of the voice channel is among the best ever reported and the reference performance under fading conditions for the high modulation modes is exceeded by far. Furthermore, synchronization in time and frequency to a real-world base station is performed what demonstrates the completeness of the PHY system.
4 Zusammenfassung Evolved EDGE ist eine Weiterentwicklung des Mobilfunkstandards der zweiten Generation (2G) mit dem Ziel einer besseren Ausnutzung des lizenzierten Spektrums, einer grösseren Zuverlässigkeit sowie einer höheren maximalen Datenrate. Dieser Fortschritt garantiert, dass das 2G System auch in Zukunft als konkurrenzfähige Backuplösung verwendet werden kann an Orten, die nicht durch 3G und 4G abgedeckt sind. Ausserdem festigt ein Ausbau des GSM/EDGE Standards seine Position als die weltweit meistverbreitetste Mobilfunklösung. Dies ist eine wichtige Eigenschaft, da weltweite Netzabdeckung eine wichtige Anforderung vieler Anwendungen im neu entstehenden Bereich der Machine-to-Machine (M2M) Kommunikation ist. Die merklich höhere Datenrate von Evolved EDGE wird erreicht indem bis zu fünf Bits pro Symbol übertragen werden. Allerdings macht diese hohe Modulationsordnung in Kombination mit der starken systemimmanenten Intersymbolinterferenz von 2G Systemen die Signaldetektion äusserst komplex. M2M Kommunikationssysteme erfordern kleine und energieeffiziente Empfänger, welche jedoch gleichzeitig die hohe Komplexität der Signaldetektion bewältigen müssen. Diese Anforderungen werden am effektivsten durch die Entwicklung von dedizierten integrierten Schaltungen (ASIC) erreicht. Optimale Algorithmen für die Signaldetektion können nur für die binäre Übertragung des ursprünglichen GSM Systems mit vernünftiger Komplexität realisiert werden. Die Demodulation von Evolved EDGE Signalen erfordert Algorithmen mit reduzierter Komplexität um kleine und energieeffiziente Lösungen zu realisieren. In dieser Arbeit werden mehrere solche Algorithmen evaluiert und im Hinblick auf eine ASIC-Implementierung optimiert. Es stellt sich heraus, dass der ix
5 x sogenannte Reduced-State Sequence Estimation (RSSE) Algorithmus mit nur 16 Trelliszuständen in Kombination mit minimalphasigem Kanalkürzungs-Filter genügt, um sehr nahe an die Leistung des optimalen Algorithmus zu gelangen. Die implementierten Architekturen des Kanalkürzungs-Filters und des RSSE-Detektors erreichen eine 5- respektive 1.6-mal bessere Hardware-Effizienz als der bisherige Stand der Technik. Darüber hinaus wird eine beträchtliche Leistungssteigerung erreicht, indem der Dekodierer zu jedem demodulierten Bit auch noch einen Wert über dessen Verlässlichkeit erhält, und die Zuverlässigkeit der Übertragung wird verbessert, wenn zwei Empfangsantennen eingesetzt werden. Eine äusserst optimierte Hardware Architektur, welche diese beiden Features beinhaltet, wird vorgestellt. Die Lösung verbessert die Fehlerrate um bis zu 10 db und weist dabei eine nur 2.5-mal schlechtere Hardware-Effizienz auf. Die Machbarkeit von Evolved EDGE wird durch die Präsentation des allerersten Basisband-Transceiver ASICs demonstriert. Der Chip wurde mit einer 130 nm CMOS Technologie hergestellt und benötigt eine Siliziumfläche von 6 mm 2. Durch die Integration des ASICs in ein komplettes Kommunikationssystem kann die Qualität der gesamten Signalverarbeitungskette, inklusive der Hochfrequenzbauteile, gemessen werden. Die gemessene Empfindlichkeit im Sprachmodus gehört zu den besten, die je publiziert wurden und die vom Standard vorgegebene Referenzleistung unter Fading-Bedingungen wird bei weitem übertroffen. Ausserdem wird die Vollständigkeit des ganzen Systems unter Beweis gestellt indem eine Zeit- und Frequenz-Synchronisation zu einer realen Basistation hergestellt wird.
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