Course DEVICES & CIRCUITS

Transkript

1 Course DEVICES & CIRCUITS Chapter: Semiconductor Memories Michael E. Auer Source of figures: Jaeger/Blalock: Microelectronic Circuit Design, McGraw-Hill

2 Course Content Introduction and Milestones in Microelectronics Solid-state Electronics Solid-state Diodes and Diode Circuits Field-effect Transistors (FET) Bipolar Junction Transistors (BJT) Integrated Transistor circuits Introduction to Digital Microelectronics NMOS Logic Circuits Complemetary MOS Logic (CMOS) Bipolar Logic Circuits Semiconductor Memories Application Specific Integrated Circuits (ASIC)

3 Chapter Content Memory Chip Organization / Speicherorganisation Static Memory Cells / Statische Speicherzellen Dynamic Memory Cells / Dynamische Speicherzellen Random Access Memory (RAM) / Speicher mit wahlfreiem Zugriff Read Only Memory (ROM) / Festwertspeicher Flip-Flops / Flip-Flops

4 Chapter Content Memory Chip Organization / Speicherorganisation Static Memory Cells / Statische Speicherzellen Dynamic Memory Cells / Dynamische Speicherzellen Random Access Memory (RAM) / Speicher mit wahlfreiem Zugriff Read Only Memory (ROM) / Festwertspeicher Flip-Flops / Flip-Flops

5 Principal Memory Architecture

6 M rows N columns Memory Chip The memory block diagram contains 2 M+N storage locations When a bit has been selected, the set of sense amplifiers are used to read/write to the memory location Horizontal rows are referred to as wordlines, whereas the vertical lines are called bitlines

7 A 256-Mbit Memory Chip 16 x128 = 2048 (2MB) The figure shows the block structure of a 256-Mb memory There are sets of column and row decoders that are used for memory array selection The column decoder splits the memory into upper and lower halves The row decoder and wordline drivers bisect each 32-Mb subarray Note that the basic building block for this memory is a 128Kb cell.

8 Bit-organized Memory

9 Word-organized Memory

10 Chapter Content Memory Chip Organization / Speicherorganisation Static Memory Cells / Statische Speicherzellen Dynamic Memory Cells / Dynamische Speicherzellen Random Access Memory (RAM) / Speicher mit wahlfreiem Zugriff Read Only Memory (ROM) / Festwertspeicher Flip-Flops / Flip-Flops

11 Static Memory Cells Inverters configured as shown in the above figure form the basic static storage building block These cross-coupled inverters are often referred to as a latch or R-S-Flip-Flop

12 VTC of Static Memory Cells The previous latch has only two stable states and is termed bistable However, it is possible for it to be held at an unstable equilibrium point where slight changes in the voltage will cause it to latch in one of the stable states

13 The 6-Transistor Cell Transfergate

14 Read Operation of a 6-Transistor Cell Final read state condition of the 6-T cell Waveforms of the 6-T cell read operation Reading a 6-T cell that is storing a 1 follows the same concept as before, except that the sources and drains of the WL transistors are switched The delay is approximately 20ns for this particular cell.

15 Write Operation of a 6-Transistor Cell While writing a 0 to a cell that is storing a 1, the bit lines must be able to overpower the output drive of the latch inverters to force it to store the new condition It can be seen that not much happens while writing a 0 or 1 into a cell that already stores a 0 or 1.

16 Chapter Content Memory Chip Organization / Speicherorganisation Static Memory Cells / Statische Speicherzellen Dynamic Memory Cells / Dynamische Speicherzellen Random Access Memory (RAM) / Speicher mit wahlfreiem Zugriff Read Only Memory (ROM) / Festwertspeicher Flip-Flops / Flip-Flops

17 Dynamic Memory Cells The 1-T cell uses a capacitor for its storage element (data is represented as either a presence or absence of a charge) Due to leakage currents of M A, the data will eventually be corrupted, hence it needs to be refreshed

18 Data Storage in a 1-T Cell Storing a 0 Storing a 1 V C = V G - V TN

19 Sense Amp for a 6-T Cell M PC is the precharge transistor whose main purpose is to force the latch to operate at the unstable point previously mentioned. The same sense amplifier used in the 6-T cell can be used for the 1-T too.

20 Address Decoders (1) NMOS Transfer Gate Decoder (Principle) Complete 3-bit CMOS Decoder

21 Address Decoders (2) 3-bit column data selector using pass-transistor logic

22 Chapter Content Memory Chip Organization / Speicherorganisation Static Memory Cells / Statische Speicherzellen Dynamic Memory Cells / Dynamische Speicherzellen Random Access Memory (RAM) / Speicher mit wahlfreiem Zugriff Read Only Memory (ROM) / Festwertspeicher Flip-Flops / Flip-Flops

23 Random Access Memory Random Access Memory (RAM) refers to memory in a digital system that has both read and write capabilities Static RAM (SRAM) is able to store its information as long as power is applied, and it does not lose the data during a read cycle Dynamic RAM (DRAM) uses a capacitor to temporarily store data which must be refreshed periodically to prevent information loss, and the data is lost in most DRAMs during the read cycle SRAM takes approximately four times the silicon area of DRAM

24 Timing Static RAM

25 Timing Dynamic RAM

26 Chapter Content Memory Chip Organization / Speicherorganisation Static Memory Cells / Statische Speicherzellen Dynamic Memory Cells / Dynamische Speicherzellen Random Access Memory (RAM) / Speicher mit wahlfreiem Zugriff Read Only Memory (ROM) / Festwertspeicher Flip-Flops / Flip-Flops

27 Read-Only Memory (ROM) The basic structure of the NMOS static ROM is shown in the figure The existence of an NMOS transistor means a 0 is stored at that address otherwise a 1 is stored The major downfall to this particular circuit is that it dissipates a lot of power

28 Read-Only Memory The main problem with these previous ROMs is that they must be designed at the mask level, meaning that it is not a versatile product. To solve this problem, the programmable ROM (PROM) was introduced. The standard PROM cannot be erased, so the erasable ROM (EPROM), and later, electrically erasable ROM (EEPROM) were introduced. High density flash memories allow for electrical erasure and reprogramming of memory cells.

29 PROM Bauelemente und Schaltungstechnik

30 Flash Memory

31 Flash Memory Cell Write Read

32 Chapter Content Memory Chip Organization / Speicherorganisation Static Memory Cells / Statische Speicherzellen Dynamic Memory Cells / Dynamische Speicherzellen Random Access Memory (RAM) / Speicher mit wahlfreiem Zugriff Read Only Memory (ROM) / Festwertspeicher Flip-Flops / Flip-Flops

33 RS Flip-Flop The reset-set (RS) flip-flop can be easily realized by using either two cross-coupled NOR or NAND gates The RSFF has the following truth tables NOR RSFF R S Q Q 0 0 Q Q NAND RSFF R S Q Q 0 0 Q Q

34 CMOS RS Flip-Flop NOR RSFF NAND RSFF

35 D-Latch using T-Gates A very important circuit of digital systems is the D-Latch which is used for a D Flip-Flop Whenever clock C goes high in the D-Latch, the data on D is passed through to Q

36 Master-Slave D Flip-Flop By using series D- Latches that latch the data on opposite clock phases, a master-slave D flip-flop can be realized

37 Summary Basic memory circuits are the random-access memory (RAM) and the read-only memory (ROM). Static RAM cells are used in SRAMs,where the integrity of the stored data is maintained as long as power is applied to the circuit. Dynamic RAM cells are utilized in most high-density dynamic RAM (DRAM) designs. Dynamic memory circuits store the information temporarily as the charge on the capacitor. Therefore the data must be periodically refreshed. Read operations also destroy the data in the cells. The structure of read-only memories (ROM) is very similar to that of RAM, but the data is embedded in the physical design of the circuitry. Bistable storage elements based on the cross-coupled inverter pair are the RS-Flip-Flop, the D latch and the master-slave flip-flop. The bistable latch forms the heart of many sense amplifier circuits to represent the binary data.