Father of most computers is the classic universal computing automaton

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1 1.1 Von Neumann Architecture Folie 1 Father of most computers is the classic universal computing automaton Basic idea postulated in a concept paper by John v.neumann First Draft of a Report on the EDVAC. Moore School, University of Pennsylvania, Reprinted in IEEE Annals on the History of Computing, No. 4, Implemented as IAS-(Institute of Advanced Studies)-Rechner (Burks, Goldstine, John von Neumann at Princeton, 1946) Preliminary Discussion of the Logical Design of an Electronic computer Instrument. Report prepared for U.S. Army Ordnance Dept., 1946, reprinted Despite huge techological changes, the basic principle is still found in modern microprocessors today

2 1.1 Von Neumann Architecture Folie 2 Concept is based on four principles 1. Computer consists of 4 units Control Unit Control Unit is interpreting programs Memory Unit Main Memory for program and data Executes arithmetical and logical operations Compute Unit I/O Units communicates with outside world Also: Secondary Memory (e.g. hard disk) In-/Out Unit

3 1.1 Von Neumann Architecture Folie 3 2. Computer is independent of the problem it is supposed to solve: computer is controled by programs Controled by program Data HW-Programming (fixed!) sequence of arithmetical and logical functions Result Instructions Instruction Interpreter (Control Unit) Control Signals Data General purpose arithmetical and logical functions Results

4 1.1 Von Neumann Architecture Folie 4 3. Program and data are located in the same memory. In theory they can be modified by the computer (Note: it is not common to modify program data during program execution) 4. Main Memory is divided into cells of equal size and sequentially numbered (memory address). Data and instructions are referenced by memory addresses 5. A program consists of a sequence of instructions, which are executed sequentially per default

5 1.1 Von Neumann Architecture Folie 5 6. Exception from sequential execution of instructions by means of conditional and unconditional branch (jump) instructions Causes jump to the addressed cell in main memory Conditional branches depend on the result of arbitrary operations 7. The computer uses binary numbers

6 1.1 Components (1) Folie 6 Control Unit Microprogramming ISA Instruction Set Architectures Memory and Register Addressing Compute Unit (also: Arithmetical Logical Unit ALU) Integer and Floating Point Units Memory Unit Memory Hierarchy Internal and External Memory Organization I/O Unit Communication via Networks/Busses

7 1.1.1 Microprogramming (1) Folie 7 Mikroprogram Mention for the first time by M.V. Wilkes (early 1950s) Itself an von Neumann Architecture Breakthrough 1964 (IBM System/360) Why Microprograms? Semantic Gap Memory was rare and expensive in the early days Flexibility Microprograms Sequence of Microinstructions

8 1.1.1 Microprogramming (2) Folie 8 Microprogram vs. Computerprogram To avoid confusion with nomenclature Programming of Computer through Instructions Assembly instructions (add, sub, mul), to distinguish them from microinstructions, we call call them macroinstructions Microprogramming of a Computer via Firmware Firmware = Set of all Microprograms Microprogram = Sequence of Microinstructions One assembly/(macro)instruction is mapped to a microprogram, which is made up of several microinstructions

9 1.1.1 Microprogramming (3) Folie 9 Relation Macroinstruction Microprogram/Microinstruction Macroinstruction is entry into a microprogram A Microprogram can include branches Microprogram (Macro-) Instruction Microinstr. 1 Microinstr. 2 Microinstr. 3 Microinstr. n

10 1 Base Components of a Computer Microprogramming (4) Question: How is a (Macro-)program mapped to a semantically equivalent series of microprograms? Folie 10

11 1.1.1 Microprogramming (5) A Control and Compute Unit is required Control Unit Load B Load A A + B A - B B - A A Load C Select Adder Select Input Select Memory Load D Load E Select C Select D Select Memory Select Output B Adder Folie 11 C A D E Input From Memory To Memory Output

12 1.1.1 Microprogramming (6) Folie 12 Execution of the following Macroinstruction A B A Which Microinstructions are necessary? Which Control Signals must be set? Select Output Select Memory Secelt D Select C Load E Load D Select Memory Selet Input Select Adder Load C A B-A A-B A+B Load A Load B Micro- Instructions Load A-B -> C; go to Mikroinstruction 2 Load C -> A; go to Mikroinstruction 3

13 1.1.1 Microprogramming (7) Folie 13 What about Branches? cf. Slide 10; Instruktion 19 Control Unit has to be extended Address of next Instruction in F Jump if C < 0 17 Sign bit of C +1 Adder F

14 1.1.1 Microprogramming (8) Folie 14 Extention in Detail: C < 0 sign bit C = 1 if (C < 0) then F = F else F = F + 1 ; Jump if C < 0 Sing bit of C Adder Address of next Microinstruction F

15 1.1.1 Microprogramming (9) Folie 15 Microinstruction Sequence with Branch Micro- Instructtions Jump, if C < 0 Select Output Select Memory Select D Select C Load E Load D Select Memory Select Input Select Adder Load C A B-A A-B A+B Load A Load B A-B -> C and D; goto microinstruction 2 if C < 0; goto microinstruction 4 D -> E; goto microinstruction 4

16 1.1.1 Microprogramming (10) (Vertical) Coding of Control Signals Vertically coded Control Signals Signals for Decoder Decorer Signals for Control Unit Load Load Load Adder Adder Memory Output Select Register Jump Load B Load A Load C Load D Load E Select Memory Select Output A + B A - B B - A A Select Adder Select Input Select Memory Select C Select D Jump, if C < 0 Folie 16

17 1.1.1 Microprogramming (11) Coding of Control Signals Control Signals Branch Select Register Output Memory Adder Adder Load Load Load Micro- Instructions A-B -> C; go to microinstruction 2 A-B -> D; go to microinstruction 3 if C < 0; go to microinstruction 5 D -> E; go to microinstruction 5 End 4 Folie 17

18 1.1.1 Microprogramming (12) Folie 18 Architecture of a microprogrammed Architecture (CAR) Control Address Register: contains address of next instruction (CBR) Control Buffer Register: contains data from microprogram Sequencing Logic Generates Read Signals Decides from where to take next address

19 1.1.1 Microprogramming (13) Folie 19 Horizontal Microprogramming Horizontal Microinstruction extended with branch address System Bus: Connects all components Internal CPU signals: wires that directly connect to the ALU and instruct it to perform operations Indirect bit: indicates whether indirect addressing is used/not used

20 1.1.1 Microprogramming (14) Folie 20 Vertical Microprogramming Vertical Microinstruction with Branch Address Instead of using control signals directly, a decoder, which creates the action microinstructions is used Advantage/Disadvantage More compact representation at the cost of additional decoder logic

21 1.1.1 Microprogramming (15) Folie 21 Overview of functions of a microprogrammed control unit

22 1.1.1 Microprogramming (16) Folie 22 (External) Interrupt Handling and Indirect Addressing Modify instruction cycle Division in several states Fetch, Execute, Indirect Addressing, Interrupt

23 1.1.1 Microprogramming (17) Folie 23 Instruction Cycle (More detailed) Takes indirect addressing and interrupts into account

24 1.1.1 Microprogramming (18) Folie 24 Organisation Control Memory Fixed Sequence of Microinstruction, which implement the previously shown instruction cycle Tasks Instruction Fetch, checking for indirect addressing and interrupt are implemented as microprograms Fixed microprograms, that cannot be changed Starting with AND microprogram are the instructions that implement actual instruction New Microprograms (new Macroinstructions) can be added by means of firmware update

25 1.1.1 Microprogramming (19) Folie 25 Summary: Advantages Microprogramming Microprogram Memory can be changed Leads to higher flexibility Instruction (Set) Compatibility New processor can understand old instructions (can be implemented as different microprogram) Instruction Emulation Processor can understand instruction set of another architecture Idea: Don t use Microprogram Memory for Instruction Translation. Use Software instead Principal Idea behind Virtual Machines

26 1.1.2 Interrupt Handling Folie 26 Simplified Interrupt Handling Instruction with magical address Save_Address MAR Save_Address What is Save_Address? stack_pointer, pointing to a special designated memory on the stack

27 1.1.2 Interrupt Handling Folie 27 State before Interrupt Address Main Memory 73 Program CPU P Interrupt- Handler A B C D Register Re Data Stack Program Counter PC 73

28 1.1.2 Interrupt Handling Folie Incoming Interrupt 2. Back up PC onto Stack 3. Load address of first instruclon of interrupt handler to PC Interrupt-Id = 158 = address for instrcution of interrupt routine CPU 158 Adresse 73 Main Memory Program P Interrupt- Handler A B C D Register Re Data Stack Program Counter PC 73

29 1.1.2 Interrupt Handling Folie 29 Address of Interrupt RouLne loaded into PC Adresse Main Memory Program CPU 158 P Interrupt- Handler A B C D Register Re Data Stack Program Counter PC

30 1.1.2 Interrupt Handling Folie Back up contents of CPU registers onto stack push A push B push C push D CPU Addresse Main Memory Program P Interrupt- Handler A B C D Register Re Data Stack Program Counter PC

31 1.1.2 Interrupt Handling Folie Complete Interrupt RouLne Main Memory Addresse Program P Interrupt- Handler CPU A B C D PC Register xxxx xxxx Re xxxx xxxx Program Counter xxxx Data xxxx xxxx Stack

32 1.1.2 Interrupt Handling Folie 32 Main Memory pop D pop C pop B pop A pop PC Program P Interrupt- Handler CPU A B C D PC Register Re Program Counter Data Stack

33 1.1.2 Interrupt Handling Folie 33 State is now the same as before interrupt Addresse Main Memory 73 Program CPU P Interrupt- Handler A B C D Register Re Data Stack Befehlszähler PC 73

34 1.1.2 Interrupt Handling Folie Increment PC and conlnue program CPU Addresse Main Memory Program Data P Interrupt- Handler A B C D Register Re Data Stack Program Counter PC 74