Verteilte Systeme Seminar

Transkript

1 Verteilte Systeme Seminar Institut für Technische Informatik TU Graz o.univ.-prof. Dr. Reinhold Weiss SS 2010 Thema: Multicore DSPs Teilnehmer Thomas Andergassen Christian Dragatin Sead Harmandic Mirza Plevljak Gerhard Scheikl

2 Introduction Architecture Memory System Market Survey A survey on multicore processors Thomas Andergassen Christian Dragatin Gerhard Scheikl Institute for Technical Informatics 21. Juni 2010

3 Introduction Architecture Memory System Market Survey Definition A multi-core processor can be described as an integrated circuit to which two or more individual processors (called cores) have been attached.

4 Introduction Architecture Memory System Market Survey Intel Nehalem Die

5 Introduction Architecture Memory System Market Survey Terminology What means processor? CPU - central processing unit DSP - digital signal processor SoC - system-on-a-chip

6 Introduction Architecture Memory System Market Survey Motivation CPU Why extend conventional uniprocessor? raw performance clock speed power consumption cooling

7 Introduction Architecture Memory System Market Survey Motivation DSP Why extend digital signal processors? Traditionally one general-purpose control core marshaled many special purpose application-specific integrated circuits (ASICs) as part of a system on chip. support numerous codecs support applications with different characteristics

8 Introduction Architecture Memory System Market Survey Bet On The Wrong Horse? This approach represents a significant gamble because parallel programming science has not advanced nearly as fast as our ability to build parallel hardware.

9 Introduction Architecture Memory System Market Survey Architecture Classification application class data processing dominated control processing dominated power / performance accelerators / integrated peripherals processing elements memory system

10 Introduction Architecture Memory System Market Survey Application Class - Data Processing Dominated Many of the classic signal processing algorithms are part of this group: graphics rasterization image processing audio processing wireless baseband processing Typically a sequence of operations on a stream of data with little or no data reuse. Operations can frequently be performed in parallel. High throughput and performance required.

11 Introduction Architecture Memory System Market Survey Application Class - Control Processing Dominated The code tend to be dominated by conditional branches, complicating parallelism. file compression / decompression network processing transactional query processing Programs need to keep track of large amounts of state and often have a high amount of data reuse. These types of applications favor a more modest number of general-purpose processing elements.

12 Introduction Architecture Memory System Market Survey Application Class Challenge In almost all cases, no application can fit into these neat divisions, but execution phases of an application may. H.264/AVC video codec: data dominant when performing the block filter control dominated when compressing or decompressing video

13 Introduction Architecture Memory System Market Survey Power / Performance mobile devices: strict power budget, but certain performance necessary server: power consumption is an expense factor

14 Introduction Architecture Memory System Market Survey Accelerators / Integrated Peripherals Accelerators or integrated peripherals are typically ASICs or highly specialized processors that can not be efficiently emulated by software. rasterizers codec accelerators memory controllers etc. Small contributors to power consumption. Large impact on overall performance possible.

15 Introduction Architecture Memory System Market Survey Architecture

16 Introduction Architecture Memory System Market Survey Processor Architecture ISA - Instruction Set Architecture Set of Instructions a Architecture understands Multi-core processors use same ISA as Single Core (with minor modifications) RISC - Reduced Instruction Set Few simple instructions Many registers Big code Easier to design Cheaper to produce All instructions same length CISC - Complex Instruction Set Many powerful instructions Few registers, cause register address part of instruction Compact Code Instructions as Microcode (flexible, changeable, but little slower) Slow decoding of complex instructions of variable size

17 Introduction Architecture Memory System Market Survey 6502(RISC) vs Z80(CISC) CISC: Z80 Successor on Basis 8080, 1975 price of 175 Dollars 1 Accumulator, 6 8-Bit registers that can be combined to 4 16-Bit registers 16 Bit stack pointer and Program Counter 134 commands Instruction from 1 to 5 Byte, decoding 4 to 28 Cycles first 3-4 MHz then up to 10 MHz RISC: 6502 Examples: Atari VCS 2600, C64, Apple II 1975 price of 25 Dollars 3 8-Bit registers 8-Bit stack pointer Instruction decoding 1-2 Cycles High performance cause RAM faster then processor 1-2 MHz Performance increase stopped cause of slow RAM Still produced today (up to 14MHz)

18 Introduction Architecture Memory System Market Survey List of Processor Architectures X86(CISC) ia32 (i386, Pentium, Athlon) x86-64 (64-bit superset of IA-32) Sparc(RISC) Power Architecture(RISC) Power PowerPC MIPS(RISC) AVR(RISC) ARM(RISC) 68000(CISC) System/360(CISC) Transputer, Multiprocessor 1985 (RISC)

19 Introduction Architecture Memory System Market Survey Trend to ISA extensions Trend to base ISA with extensions Popular Extensions Pentium MMX, MMX2, SSE1-5 Athlon 3DNow! Power PC Altivec ARM NEON Multimedia extension VIA Padlock Engine Better performance/power ratio Multiple operations in with one instruction enables features the normal CPU would not be fast enough Applications Multimedia(eg MPEG decoder,...) Security(SSL unit, AES unit,...) Signal Processing Extensions for parallel processing in data dominated processing

20 Introduction Architecture Memory System Market Survey Microarchitecture Components to implement the ISA Same ISA can be made by different components, eg. Pentium and Athlon implement x86 with different components Decisive for multi core performance Usually same cores in homogeneous architecture Heterogeneous architecture can result in better power/performance ratio but complicated programming model

21 Introduction Architecture Memory System Market Survey Pipeline Abbildung: Pipeline A IF, Instruction Fetch, instruction fetched from Memory B ID, Instruction Decoding, instruction gets decoded, and data is fetched from memory and/or registers C EX, Execution, instruction gets executed and buffered in pipeline-latch D WB, Write Back, result written back in memory and/or registers

22 Introduction Architecture Memory System Market Survey Pipelining Pipelining brings performance But complexity grows greater than quadratically with every new pipeline More, simpler pipeline steps for higher frequency ARM7TDMI(-S) 3 steps ARM9TDMI 5 steps XScale PXA210/PXA250 7 steps NetBurst (Prescott, Cedar Mill) 31 steps Intel Core 14 steps Intel Atom 16 steps UltraSPARC T1 6 steps Xelerator X10q over 1000 steps Pipeline Hazards: Resource hazards - pipeline step needs resource that is blocked by another pipeline step Data hazards - data or register content that are needed by a step are not available Control-flow hazards - pipeline has to wait if conditional jump occurs or not Need for excellent branch-prediction

23 Introduction Architecture Memory System Market Survey in order processing and out of order processing In order processing: Instruction Fetch, Instruction Decode, Execution, Write Back Uses low power, low to medium complexity, smaller die area But low to medium single thread performance Out of order processing: Instruction fetch. Instruction gets decoded and queued Instruction waits in the queue until its input operands are available. Instruction is allowed to leave the queue before older instructions. Instruction gets executed Results are queued. Only after all older instructions have their results written back, then this result is written back. Used to optimize the pipeline Very fast single thread performance Needs high power, has high design complexity, needs bigger die area

24 Introduction Architecture Memory System Market Survey SIMD SIMD: Single Instruction Multiple Data also known as Array Processor or Vector Processor Used for parallel elaboration of data (with single command) Registers split into lanes used for eg. matrix operations Applications like image and audio processing, multimedia,... Used in many modern processors like Pentium, PowerPc,... Special instruction needed, so ISA extension like SSE, 3DNOW or ALTIVEC Reach from simple binary or calculation operations to complex DSP operations Good performance/power ratio Inefficient for general purpose processing Can not be used if code can not be vectorized

25 Introduction Architecture Memory System Market Survey SIMD/MIMD MIMD: Multiple Instruction, Multiple Data multiple operations on multiple input streams One CPU for control strictly coupled like multiprocessor or single graphic card loosely coupled like multicomputer or SLI/Crossfire can unroll loops and distribute them over hundreds of ALU s typically in stream processors, like graphic processors Trend to APU (CPU/GPU integration) needs special instructions high level libraries like CUDA, STREAM

26 Introduction Architecture Memory System Market Survey VLIW VLIW: Very Long Instruction Word Uses multiple pipelines Without hazard detection logic, forwarding, scheduling Complexity moved to compiler Compiler optimizes code, not dynamically optimized at runtime But no performance gain if compiler can not find parallelizable code Good performance/power ratio

27 Introduction Architecture Memory System Market Survey Simultaneous Multi Threading or Hyper Threading Intel started SMT in 2005 Use of 2 pipelines in 1 processor Three types of resources Replicated resources: registers, stack-pointer and program-counter Partitioned resources: Available once but partitioned: instruction queues, reorder buffer, load/store buffer. Shared resources: everything else, including ALUs and FPU. Target is better load of shared FPU and ALU Also present in embedded systems Ubicom 5K Familie (10 Threads) MIPS 34K Familie (5 Threads) Innovasic fido 1100 (one CPU with 5 Threads, 4 additional I/O-Processors) Scheduling often not easy, can result in worse performance if threads are ported to cores with high load SMT Parking: virtual cores only used if physical cores are under high load

28 Introduction Architecture Memory System Market Survey Hyper Threading Problems under Vista Abbildung: Hyper Threading Movie Maker Benchmark Vista

29 Introduction Architecture Memory System Market Survey Hyper Threading Problems under Vista Abbildung: Hyper Threading Winrar Benchmark

30 Introduction Architecture Memory System Market Survey Real Multi-core Multiple complete cores in 1 processor No shared processing units Shared main memory and (some) caches Higher complexity in intra chip communication Higher complexity in memory model

31 Introduction Architecture Memory System Market Survey Memory system

32 Introduction Architecture Memory System Market Survey Memory system Cache Single-Core: simple component few levels Multicore: just one part of the system consistency model cache coherence intrachip interconnect

33 Introduction Architecture Memory System Market Survey Consistency model reordering of operations programming effort code scheduling

34 Introduction Architecture Memory System Market Survey Consistency model Weak: explicit code scheduling complex synchronization protocols Strong: less effort simpler synchronization strict ordering constraints (ie. sequencial consistency) Consistency models effect performance!

35 Introduction Architecture Memory System Market Survey Memory consistency

36 Introduction Architecture Memory System Market Survey Cache configuration high bandwith local memory low-bandwith off-chip memory tagged and managed by hardware explicitly managed local store memory

37 Introduction Architecture Memory System Market Survey Automatically tagged caches most common form transparent to the instruction stream like access to one uniform memory Drawbacks nondeterministic performance die area for storing tags

38 Introduction Architecture Memory System Market Survey Local stores deterministic performance managed explicitly more storage for same area (no tags) Drawbacks complex software management only preferred for hard realtime

39 Introduction Architecture Memory System Market Survey Cache amount application dependent bigger caches better performance large caches not useful for streaming applications sometimes two cache modes possible cache usually as big as area and power budget allow

40 Introduction Architecture Memory System Market Survey Cache levels depending on how far main memory is away (cycles) subsequent levels: larger/slower/shared provides illusion of a very fast memory AMD Phenom: at lease 3 levels embedded mulitcores: sometimes only one level higher clocked embedded processors caches get more important

41 Introduction Architecture Memory System Market Survey Intrachip interconnect Possible implementations: Bus: simple but bandwith/latency limited crossbar ring NoC (network on chip): good scaling, hard to design Also provides cache coherence.

42 Introduction Architecture Memory System Market Survey Cache coherence Broadcast-based simple only one processor operating visible to all write invalidates read

43 Introduction Architecture Memory System Market Survey Cache coherence Directory-based scales better distributed directory allows multiple actions concurrently for access: query home node lack of cache coherence software must handle it!

44 Introduction Architecture Memory System Market Survey Cache coherence

45 Introduction Architecture Memory System Market Survey Market Survey

46 Introduction Architecture Memory System Market Survey GENERAL-PURPOSE SERVER AND MOBILE/EMBEDDED MULTICORES The microarchitecture of their cores is traditional and based on a powerful conventional uniprocessor. These chips are intended for applications found in the desktop and server markets. Authorized licensed use limited to: Technische Universitaet Graz. Downloaded on March 12,2010 at 1 IEEE SIGNAL PROCESSING MAGAZINE [32] NOVEMBER 2 [TABLE 3] TABLE OF GENERAL-PURPOSE SERVER AND MOBILE/EMBEDDED MULTICORES. AMD PHENOM [11], [15] INTEL CORE I7 [2], [5] SUN NIAGARA T2 [16], [17] INTEL ATOM [18], [5] ARM CORTEX- A9 [6] XMOS XS1-G4 [19] ISA MICROARCHITECTURE NUMBER OF CORES CACHE COHERENCE INTERCONNECT SOME CURRENT C In recent years, th architectures prod targeted every ma purpose desktop a this is in large part with acceptable po The first four en purpose multicores ditional and based They all employ a cores with large ca tions found in the is not an overridin are also multicore embedded applicati cores that are wel Power is an overri are intended to run consume 1 W or les The next set of specialized and are These architecture tion domain and, f bers of cores fo number is in the h erogeneous archit cialized data proce very high power ra Table 5 present ized for specific a variety. Most of t domains such as w where simple para they support high nection networks t application domai computation rates In the remaind multicores in mor tinct categories: se CONSISTENCY MODEL MAX. POWER FREQUENCY OPS/CLOCK X86 THREE-WAY OUT-OF-ORDER FOUR 64 KB IL1 AND DL1/ DIRECTORY POINT TO POINT PROCESSOR 140 W 2.5 GHZ OPS/ SUPERSCALAR, 128-B SIMD CORE, 256 KB L2/CORE, 3.0 GHZ CLOCK 2-6 MB L3 X86 FOUR-WAY OUT-OF-ORDER, TWO TO EIGHT 32 KB IL1 AND DL1/ BROADCAST POINT TO POINT PROCESSOR 130 W 2.66 GHZ OPS/ TWO-WAY SMT, 128-B SIMD CORE, 256 KB L2/CORE, 3.33 GHZ CLOCK 8 MB L3 SPARC TWO-WAY IN-ORDER, EIGHT 16 KB IL1 AND 8 KB DL1/ DIRECTORY CROSSBAR TOTAL STORE MHZ 16 OPS/CLOCK EIGHT-WAY SMT CORE, 4 MB L2 ORDERING W 1.4 GHZ X86 TWO-WAY IN-ORDER, ONE TO TWO 32 KB IL1 AND DL1/ BROADCAST BUS PROCESSOR 2 8 W 800 MHZ 2 16 OPS/ TWO-WAY SMT, 128-B SIMD CORE, 512 KB L2/CORE 1.6 GHZ CLOCK ARM THREE-WAY OUT-OF-ORDER ONE TO FOUR (16,32,64) KB IL1 AND BROADCAST BUS WEAKLY 1 W (NO N/A 3 12 OPS/ DL1/CORE, UP TO ORDERED CACHE) CLOCK 2 MB L2 XCORE ONE-WAY IN-ORDER, FOUR 64 KB LCL STORE/CORE NONE CROSSBAR NONE 0.2 W 400 MHZ 4 OPS/CLOCK EIGHT-WAY SMT Numbers are estimates because design is offered only as a customizable soft core. ACCELERATORS/I Accelerators or in highly specialized p ed by software. So codec accelerators, one of the smaller have a large impac example of accelera found on the TI OM share a limited am a practical option. marized in Table 2.

47 Introduction Architecture Memory System Market Survey HIGH-PERFORMANCE MULTICORES These architectures target high performance in their application domain and, for the most part, employ significant numbers of cores - for the AMD R700 and NVIDIA G200, this number is in the hundreds. The IBM Cell implements a heterogeneous architecture with a modest number of very specialized data processing engines. Authorized licensed use limited to: Technische Universitaet Graz. Downloaded on March 12,2010 a IEEE SIGNAL PROCESSING MAGAZINE [33] NOVEMBE [TABLE 4] TABLE OF HIGH-PERFORMANCE MULTICORES. CONSISTENCY MAX. ISA MICROARCHITECTURE NUMBER OF CORES CACHE COHERENCE INTERCONNECT MODEL POWER FREQUENCY OPS/CLOCK AMD RADEON N/A FIVE-WAY VLIW 160 CORES, 16 CORES 16 KB LCL STORE/SIMD NONE N/A NONE 150 W 750 MHZ 800-1,600 R700 [20] PER SIMD BLOCK, TEN BLOCK OPS/CLOCK BLOCKS NVIDIA G200 N/A ONE-WAY IN-ORDER 240, EIGHT CORES PER 16 KB LCL STORE/EIGHT NONE N/A NONE 183 W 1.2 GHZ OPS/ [8], [21] SIMD UNIT, 30 SIMD CORES CLOCK UNITS INTEL LARRABEE [22] X86 TWO-WAY IN-ORDER, 4-WAY UP TO KB IL1 AND 32 KB DL1/ BROADCAST BIDIRECTIONAL PROCESSOR N/A N/A 96-1,536 OPS/ SMT, 512-B SIMD CORE, 4 MB L2 RING CLOCK IBM CELL [9], [23] POWER TWO-WAY IN-ORDER, 1 PPU, EIGHT SPUS PPU: 32 KB IL1 AND 32 KB NONE BIDIRECTIONAL WEAK (PPU), 100 W 3.2 GHZ 72 OPS/CLOCK TWO-WAY SMT PPU, 2-WAY DL1, 512 KB L2; SPU: RING NONE (SPU) IN-ORDER 128-B SIMD SPU 256 KB LCL STORE MICROSOFT POWER TWO-WAY IN-ORDER, TWO- THREE 32 KB IL1 AND 32 KB DL1/ BROADCAST CROSSBAR WEAKLY 60 W 3.2 GHZ 6-24 OPS/ XENON [10] WAY SMT, 128-B SIMD CORE, 1 MB L2 ORDERED CLOCK All values are estimates as processor is not yet in production. [TABLE 5] TABLE OF DSP AND EXOTIC MULTICORES. CONSISTENCY MAX. ISA MICROARCHITECTURE NUMBER OF CORES CACHE COHERENCE INTERCONNECT MODEL POWER FREQUENCY OPS/CLOCK AMBRIC N/A ONE-WAY IN-ORDER SR, 168 SR, 168 SRD 21 KB LCL STORE/EIGHT NONE NOC NONE 6 16 W 350 MHZ 672 OPS/ AM2045 [24], [25] THREE-WAY IN-ORDER SRD CORES CLOCK ELEMENT CXI N/A ONE-WAY IN-ORDER, FOUR CLUSTERS OF 32 KB OF LCL STORE/ NONE HIERARCHIAL NOC NONE 1 W 200 MHZ 64 OPS/CLOCK ECA 64 [26], [3] DATAFLOW CONNECTIONS ONE CORE+ALUS CLUSTER (16-B)

48 Introduction Architecture Memory System Market Survey IEEE SIGNAL PROCESSING MAGAZINE [33] NOVEMBER 2009 Authorized licensed use limited to: Technische Universitaet Graz. Downloaded on March 12,2010 at 10:11:36 EST from IEEE Xplore. Restrictions apply. DSP AND EXOTIC MULTICORES [TABLE 4] TABLE OF HIGH-PERFORMANCE MULTICORES. CONSISTENCY MAX. ISA MICROARCHITECTURE NUMBER OF CORES CACHE COHERENCE INTERCONNECT MODEL POWER FREQUENCY OPS/CLOCK AMD RADEON N/A FIVE-WAY VLIW 160 CORES, 16 CORES 16 KB LCL STORE/SIMD NONE N/A NONE 150 W 750 MHZ 800-1,600 R700 [20] PER SIMD BLOCK, TEN BLOCK OPS/CLOCK BLOCKS NVIDIA G200 N/A ONE-WAY IN-ORDER 240, EIGHT CORES PER 16 KB LCL STORE/EIGHT NONE N/A NONE 183 W 1.2 GHZ OPS/ Most [8], [21] of them target data SIMD UNIT, dominated 30 SIMD CORES application domains such as wireless CLOCK UNITS INTEL LARRABEE baseband, [22] X86 TWO-WAY IN-ORDER, 4-WAY UP TO 48 and audio/visual 32 KB IL1 AND 32 KB DL1/ BROADCAST BIDIRECTIONAL PROCESSOR N/A N/A 96-1,536 OPS/ SMT, 512-B SIMD codecs CORE, 4 MB where L2 simple RING parallelism can often CLOCK be IBM CELL [9], [23] POWER TWO-WAY IN-ORDER, 1 PPU, EIGHT SPUS PPU: 32 KB IL1 AND 32 KB NONE BIDIRECTIONAL WEAK (PPU), 100 W 3.2 GHZ 72 OPS/CLOCK TWO-WAY SMT PPU, 2-WAY DL1, 512 KB L2; SPU: RING NONE (SPU) IN-ORDER 128-B SIMD SPU 256 KB LCL STORE exploited. Accordingly, they support high computation rates. MICROSOFT XENON [10] POWER TWO-WAY IN-ORDER, TWO- WAY SMT, 128-B SIMD THREE 32 KB IL1 AND 32 KB DL1/ CORE, 1 MB L2 BROADCAST CROSSBAR WEAKLY ORDERED 60 W 3.2 GHZ 6-24 OPS/ CLOCK All values are estimates as processor is not yet in production. [TABLE 5] TABLE OF DSP AND EXOTIC MULTICORES. CONSISTENCY MAX. ISA MICROARCHITECTURE NUMBER OF CORES CACHE COHERENCE INTERCONNECT MODEL POWER FREQUENCY OPS/CLOCK AMBRIC N/A ONE-WAY IN-ORDER SR, 168 SR, 168 SRD 21 KB LCL STORE/EIGHT NONE NOC NONE 6 16 W 350 MHZ 672 OPS/ AM2045 [24], [25] THREE-WAY IN-ORDER SRD CORES CLOCK ELEMENT CXI N/A ONE-WAY IN-ORDER, FOUR CLUSTERS OF 32 KB OF LCL STORE/ NONE HIERARCHIAL NOC NONE 1 W 200 MHZ 64 OPS/CLOCK ECA 64 [26], [3] DATAFLOW CONNECTIONS ONE CORE+ALUS CLUSTER (16-B) TO 15 RECONFIGURABLE ALUS TI TMS320- ARM, ONE ARM9 ONE-WAY TWO ARM9: 16 KB IL1, 8 KB NONE BUS WEAKLY 3 5 W ARM: OPS/ DM6467 [14] C64X IN-ORDER, ONE C64X DL1; C64X: 32 KB IL1 ORDERED 364 MHZ, CLOCK EIGHT-WAY VLIW AND DL1, 128 KB L2 C64X: MHZ TI OMAP ARM, TWO ARM THREE-WAY THREE N/A BROADCAST BUS WEAKLY 1 W 1GHZ 6 14O PS/ 4430 [12] C64X OUT-OF-ORDER, ONE C64X AMONG ARM ORDERED CLOCK EIGHT-WAY VLIW CORES TILERA TILE64 N/A THREE-WAY VLIW KB IL1 AND DL1/CORE, DIRECTORY NOC N/A W OPS/ [27], [28] 64 KB L2/CORE MHZ CLOCK HIVEFLEX N/A TWO-WAY VLIW CONTROL TWO TO FIVE 2X CONFIGURABLE L1 NONE BUS NONE 0.25 W 200 MHZ 2 22 OPS/ CSP2X00 [29] CORE, FIVE-WAY VLIW FOR BASE CORE, LCL CLOCK COMPLEX CORE STORE FOR COMPLEX CORE Numbers are estimates because design is offered only as a customizable soft core.

49 Introduction Architecture Memory System Market Survey Thank you for your attention

50 Introduction Architecture Memory System Market Survey References A Survey of Multicore Processors Geoffrey Blake, Ronald G. Dreslinski, and Trevor Mudge IEEE SIGNAL PROCESSING MAGAZINE [26] NOVEMBER 2009

51 Intro Architecture ARM DSP Fazit The Texas Instruments TMS320DM6467 Thomas Andergassen Christian Dragatin Gerhard Scheikl Institute for Technical Informatics 21. Juni 2010

52 Intro Architecture ARM DSP Fazit Texsas Instruments DSPs

53 Intro Architecture ARM DSP Fazit Digital Media System-on-Chip PVR construction kit ;-) DaVinci video processor technology full 1920 x 1080 HD resolution networked digital video applications cost circa $100 per plain chip

54 Intro Architecture ARM DSP Fazit TMS320DM6467T in Life Size

55 Intro Architecture ARM DSP Fazit Complete Board

56 Intro Architecture ARM DSP Fazit TMS320DM6467T Features High-Performance Digital Media SoC 1-GHz C64x+ Clock Rate 500-MHz ARM926EJ-S Clock Rate Eight 32-Bit C64x+ Instructions/Cycle 8000 C64x+ MIPS Fully Software-Compatible With C64x / ARM9 Industrial Temperature Devices Available Advanced VLIW TMS320C64x+ DSP Core Eight Highly Independent Functional Units Load-Store Architecture With Non-Aligned Support Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Additional C64x+ Enhancements C64x+ Instruction Set Features

57 Intro Architecture ARM DSP Fazit Functional Block Diagram

58 Intro Architecture ARM DSP Fazit OS and Toolchain Linux or WindowsCE on ARM with DSPLINK library/driver and HDVICP library/driver standard development tools DSP/BIOS on DSP with DSPLINK library/driver TI Code Composer Studio (CCStudio)

59 Intro Architecture ARM DSP Fazit Shared Memory between ARM and DSP DSPLINK is an interprocessor communications scheme. Implementation: pre-determined memory addresses for messages from ARM to DSP and vice versa messages sent by writing into the pre-determined address and then sending an interrupt once receiving processor has read, it sets a flag

60 Intro Architecture ARM DSP Fazit Interrupts large number of interrupts ARM (all) and DSP (some) can service these interrupts can selectively be enabled and disabled by default all enabled on ARM

61 Intro Architecture ARM DSP Fazit Interconnect ARM Core has access to following DSP Memories L1D L1P L2 DSP Core has access to following ARM Memories 32KB ARM Internal RAM on the ARM D-TCM interface

62 Intro Architecture ARM DSP Fazit Power Consumption

63 Intro Architecture ARM DSP Fazit ARM926EJ-S

64 Intro Architecture ARM DSP Fazit ARM926EJ-S EMT9 - Embedded Trace Macrocell

65 Intro Architecture ARM DSP Fazit ARM926EJ-S TCM - Tightly Coupled Memory

66 Intro Architecture ARM DSP Fazit ARM926EJ-S AMBA - Advanced Microcontroller Bus Architecture

67 Intro Architecture ARM DSP Fazit ARM926EJ-S AHB - Advanced Highperformance Bus

68 Intro Architecture ARM DSP Fazit ARM9 Features Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets DSP Instruction Extensions and SingleCycle MAC ARM Jazelle Technology (Java acceleration) EmbeddedICE-RT Logic for Real-Time Debug MMU with TLB Access to all peripherals of the DM6467

69 Intro Architecture ARM DSP Fazit ARM9 Memory architecture ARM9 Memory Architecture 16K-Byte Instruction Cache 8K-Byte Data Cache 32K-Byte RAM (two pages) 8K-Byte ROM

70 Intro Architecture ARM DSP Fazit Control coprocessor (CP15) Configuration and control of Caches Tightly-Coupled Memories (TCMs) MMU most other system options accessed by MCR and MRC instructions

71 Intro Architecture ARM DSP Fazit TLB TLB has two parts: main TLB (32 entries) lockdown TLB (8 locking entries) supports sections and pages two translation levels MMU puts translated addresses into TLB

72 Intro Architecture ARM DSP Fazit TLB Mapping sizes 1MB - sections 64KB - large pages 4KB - small pages 1KB - tiny pages

73 Intro Architecture ARM DSP Fazit TLB Features access permissions hardware page table walks invalidate TLB (entry or entire) using CP15 lockdown of TLB entries using CP15

74 Intro Architecture ARM DSP Fazit TLB Overview

75 Intro Architecture ARM DSP Fazit TLB section

76 Intro Architecture ARM DSP Fazit TLB coarse page

77 Intro Architecture ARM DSP Fazit TLB fine page

78 Intro Architecture ARM DSP Fazit TLB level 2

79 Intro Architecture ARM DSP Fazit MMU faults alignment faults (data accesses only) translation faults domain faults permission faults placed in FSR (fault status register) or FAR (fault address register)

80 Intro Architecture ARM DSP Fazit Jazelle Solution in hardware and software Direct bytecode execution JVM attempts to run bytecode in hardware complicated/less-used operations in software about 95% in hardware

81 Intro Architecture ARM DSP Fazit Jazelle Implementation low-level binary translation extra stage between the fetch and decode Recognised bytecodes are converted into native ARM instructions moves JVM interpretation into hardware

82 Intro Architecture ARM DSP Fazit Noncachable instruction fetches to increase performance speculative instruction fetching can be disabled by CP15 cache cleared at jump

83 Intro Architecture ARM DSP Fazit ICache, DCache caches virtual indes/tag DCACHE supports write-through, write-back or copy-back pseudo-random or round-robin replacement (CP15)

84 Intro Architecture ARM DSP Fazit C64+ DSP VLIW Architecture C64+ RISC-like Instruction Set Little Endian 5832 MIPS 64 general-purpose 32-bit registers lots of special instructions. needs good compiler

85 Intro Architecture ARM DSP Fazit C64x+ 8 functional units 2x MAC(.M) with following capabilities/cycle 1x 32 x 32 bit multiplication 1x 16 x 32 bit multiplication 2x 16 x 16 bit multiplication 2x 32 x 16 bit multiplication 2x 16 x 16 bit multiplication with add/subtract capabilities 4x 8 x 8 bit multiplication 4x 8 x 8 bit multiplication with add/subtract capabilities 4x 16 x 16 multiplication with add/subtract capabilities (including a complex multiply). Support for Galois field multiplication for 8-bit and 32-bit data. 2x ALU(.L) with parallel add/subtract capabilities for 32Bit or pair of 16Bit, larger arithmetic and compare operations 2x ALU(.S) for quad 8-bit/16-bit and dual 16-bit instructions. Larger bit-shifting and bit-field operations 2x DLS(.D) for data loading/storing split onto 2 datapaths by 4 functional units each

86 Intro Architecture ARM DSP Fazit Datapaths Abbildung: C64+ Datapath

87 Intro Architecture ARM DSP Fazit Pipeline Pipelinesteps for Fetch, Decode, Execute, Writeback Abbildung: Full pipeline

88 Intro Architecture ARM DSP Fazit Pipeline - Fetch 4 Fetch Steps PG: Program address generate PS: Program address send PW: Program access ready wait PR: Program fetch packet receive Abbildung: Pipeline fetch

89 Intro Architecture ARM DSP Fazit Pipeline - Decode 2 Decode Steps DP: Instruction dispatch DC: Instruction decode Abbildung: Pipeline decode

90 Intro Architecture ARM DSP Fazit Pipeline - Execute maximal 5 Execute Stufen, abhängig vom Befehl E1: For all instruction types, the conditions for the instructions are evaluated and operands are read. For load and store instructions, address generation is performed and address modifications are written to a register file. For branch instructions, branch fetch packet in PG phase is affected. For single-cycle instructions, results are written to a register file. E2: For load instructions, the address is sent to memory. For store instructions, the address and data are sent to memory. Single-cycle instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. For single 16 x 16 multiply instructions, results are written to a register file. For multiply unit, nonmultiply instructions, results are written to a register file. E3: Data memory accesses are performed. Any multiply instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs.

91 Intro Architecture ARM DSP Fazit E4: E5: Pipeline - Execute For load instructions, data is brought to the CPU boundary. For multiply extensions, results are written to a register file. For load instructions, data is written into a register. Abbildung: Pipeline execute

92 Intro Architecture ARM DSP Fazit Complete Pipeline Abbildung: Complete pipeline with Datapaths

93 Intro Architecture ARM DSP Fazit Diagram Abbildung: C64+ Diagram

94 Intro Architecture ARM DSP Fazit C64x+ Internal Memory Memory Level 1 Program RAM, 32KB, mapped memory or directly mapped cache Freeze Mode when configured as Cache Global Coherence Block Coherence Level 1 Data RAM, 32KB, mapped memory or 2-way set associated cache Writeback Cache Freeze Mode when configured as Cache Global Coherence Block Coherence Level 2 RAM, 128KB, mapped memory, cache or combination of both

95 Intro Architecture ARM DSP Fazit C64x+ Memory Controller Controller Unified Memory Controller Program Memory Controller Data Memory Controller External Memory Controller Internal Direct Memory Access Channel 0 - Memory to CFG Channel 1 - Memory to Memory

96 Intro Architecture ARM DSP Fazit Diagram Abbildung: C64+ Diagram

97 Intro Architecture ARM DSP Fazit C64x+ features SPLOOP: A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. for(int i=0;i 100);i++) dest[i]=source[i]; Implemented in Hardware Loop buffer Loop buffer count register (LBC) Inner loop count register (ILC) Reload inner loop count register (RILC) Task state register (TSR) Interrupt task state register (ITSR) NMI/Exception task state register (NTSR)

98 Intro Architecture ARM DSP Fazit C64x+ features Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

99 Intro Architecture ARM DSP Fazit Thank you for your attention

100 Intro Architecture ARM DSP Fazit References TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide TEXAS INSTRUMENTS Low power consumption and a competitive price tag make the six-core TMS320C6472 ideal for high-performance applications Loc Truong TEXAS INSTRUMENTS TMS320DM6467 Digital Media System-on-Chip SPRS403F DECEMBER 2007 REVISED OCTOBER 2009 TEXAS INSTRUMENTS

101 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Trends in Multicore DSP Platforms Thomas Andergassen Christian Dragatin Gerhard Scheikl Institute for Technical Informatics 21. Juni 2010

102 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Overview HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS

103 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Overview HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS

104 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Overview HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS

105 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Overview HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS

106 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Introduction

107 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Multicore DSPs gained significant importance video applications high-speed internet on mobiles increased performance lower cost and power consumption

108 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Embedded processing previous: multicore on board/system size limitations 1/2/4 cores recently: new semiconductor processes

109 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Embedded processing single-chip DSPs become multicore size/power consumption/performance picochip: >300 cores SoC

110 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Cooling generally forced air avoid a fan if possible fan-cooled ACTA carrier card: up to 200W cheapest board-level solution: power dissipation about 10W per chip

111 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Historical Perspectives concept of DSPs: mid-1970s research centers solve real-world problems using computers non-real-time

112 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Speak & Spell 1978 single integrated circuit synthesize speech digital signal processing in real-time DSPs can be const-effective Begin of DSP-era

113 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Difference to Microprocessors complex math guaranteeing real-time dual/multiple data buses logic to prevent over/underflow

114 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Difference to Microprocessors single cycle complex instructions hardware multiplier little or no capability to interrupt special instructions to handle signal processing

115 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Customer Question If I can t do it with one DSP, why not use two of them? How do I squeeze my algorithm into this device floating-point DSPs significantly more performance customers used multiple DSPs working together

116 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Samples/s

117 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS MMAC/s

118 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Architecture 2008: 68% of DSPs in wireless sector mobile handsets base stations new demands: mobile TV/internet 3G, WiMAX performance, power consumption, space

119 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Typical multicore DSP platform

120 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Interconnect hierachical mesh

121 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Hierachical network CPUs with need of low latency and high bandwidth placed together on a shared switch shared switches are connected memory shared and local complex memory map

122 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Mesh network 2D-array of nodes network of busses/simple switching units scale to large numbers without increase of complexity

123 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Existing vendor-specific multicore DSP platforms

124 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Texas Instruments hierarchical interconnect heterogenous MC DSP homogeneous MC DSP TNETV3020: 6x TMS320C64x at 500Mhz consuming 3.8W/core TMS320TCI6488: 3x TMS320C64x at 1Ghz TNETV3010: 6x TMS320C55x at 300Mhz consuming 1.2W/core targeting audio and video applications

125 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Texas Instruments TNETV3020 Abbildung: TI TNETV3020

126 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Freescale Starcore DSP MSC8112 2x SC140 DSP MSC8156 4x SC3400 DSP MSC3850 6x SC3850 DSP up to 1Ghz LTE, WiMax, 3GPP/3GPP2 Homogeneous hierarchical interconnect architecture with chip level arbitration and switching Large memory, up to 0.5GB per controller, 400/800Mhz DDR Maple B and viterbi decoder

127 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Freescale 8156 Abbildung: Freescale 8156

128 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Picochip mesh interconnect homogeneous PC203 heterogenous PC205 with ARM926EJ-S-Core and Pico Array with 248 VLIW DSP Processors WiMax, HSDPA, WCDMA, advanced wireless protocols

129 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS picochip PC205 Abbildung: picochip PC205

130 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS picochip picoarray Abbildung: picochip picoarray

131 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Tilera TILEPro36 TILEPro64 TILE64 64 identical tiles in 8x8 grid every tile has 4 cores, L1 and L2 Cache and a non blocking switch Mhz, 15-22W advanced networking, telecommunication, digital video

132 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Tilera Tile64 multicore DSP Abbildung: Tile64 multicore DSP

133 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Sandbridge heterogenous SB3011 ARM926EJ-S core 4x DSP 600MHz at 0.9V Up to 32 independent instruction streams SIMD datapath Software-defined radio Runs linux Can be programmed in high level languages like C, C++, or Java

134 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Chip comparison Abbildung: Overview

135 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Multicore DSP platform performance analysis Benchmark suites to analyze performance Benchmarking of multicore significantly more complicated then singlecore Benchmark affected by core, but also of memory and interconnect Different programming tools for any platform Different architectures Maybe doesn t fit usecase of test candidate Benchmark suites for multicore remains an active field of study Currently use of simplified benchmarks used for singlecore systems

136 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Berkley Design Technology Inc. Developed for singlecore Orthogonal frequency division multiplexing (OFDM) benchmark Simplified digital signal processing path for a fast Fourier transform(fft)-based OFDM receiver Includes a cascade of a demodulator, finite impulse response (FIR) filter, FFT, slicer, and Viterbi decoder Does not include: interleaving, carrier recovery, symbol synchronization, and frequency-domain equalization

137 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Benchmark Result PROCESSOR CLOCK(MHZ) DSP CORES ODFM CHANNELS TI TMS320C LOWEST Freescale MSC LOW Sandbridge SB MEDIUM picochip PC HIGH Tilera Tile HIGHEST

138 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS DSP PROGRAMMING IS HARD REAL-TIME step trough programs, instruction by instruction virtual multicore platforms and simulators real-time debugging for timing behavior chip level debug techniques hardware supported visualization tools

139 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS ETB (EMBEDDED TRACE BUFFER) on-chip buffer stores data generated by the ETM (at system clock rate) later read by debugger (at reduced clock rate)

140 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS OS DSP/BIOS installed on each core message passing programming model for programmer: island with bridges SMP LINUX (Symmetric MultiProcessing) installed on one core global tables, one global state shared by tasks on different cores for programmer: global view

141 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS VIRTUALISATION VMs (Virtual Machines) VMM (Virtual Machine Manager) best of two worlds DSP/BIOS concurrently with SMP LINUX

142 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS MULTICORE FOR MOBILE APPLICATION PROCESSORS TI OMAP (Open Multimedia Application Platform) Nokia Nseries multimedia smartphones SoC multicore with heterogeneous ARM + DSP each core with unique function master/slave programming paradigm most common multicore in embedded space

143 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS MULTICORE FOR CORE NETWORK TRANSCODING host processor + multiple DSPs master/slave programming paradigm each task can run on single DSP host processor as loadbalancer challenge in access of shared resources

144 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS AGERE SP2603

145 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS MULTICORE FOR BASE STATION MODEMS UMTS to HSDPA to HSUPA some DSPs and significant shared resources Fixed-Point Digital Signal Processors each core unique functionality: transmit receive symbol rate processing in late 1990s new approaches tried out: arrays of ALUs with a central controller arrays of small CPUs tightly connected but communicate synchronized

146 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS TI TCI6487

147 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS NEXT GENERATION MULTICORE DSPs I ASIC (Application-Specific Integrated Circuit) SDR (Software Defined Radio)

148 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS NEXT GENERATION MULTICORE DSPs II AsAP (Asynchronous Array of simple Processors) optimized for dataflow mesh network with very small cores with minimal memory per core each core own clock generator cores communicate asynchronously by doubly clocked FIFO buffers challenge to create the necessary software tools

149 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS AsAP PROCESSOR ARCHITECTURE

150 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS CONCLUSION Parallelization of DSP algorithms is often possible in a deterministic manner using data flow diagrams. Hence, fast development of DSP multicores!

151 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS Thank you for your attention

152 HISTORY ARCHITECTURE SOFTWARE TOOLS APPLICATIONS References Trends in Multicore DSP Platforms Lina J. Karam, Ismail AlKamal, Alan Gatherer, Gene A. Frantz, David V. Anderson, and Brian L. Evans IEEE SIGNAL PROCESSING MAGAZINE [38] NOVEMBER 2009

153 TOMAHAWK VisoMT Reliability AK Multicore Thomas Andergassen Christian Dragatin Gerhard Scheikl Institute for Technical Informatics 21. Juni 2010

154 TOMAHAWK VisoMT Reliability A Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for Software Defined Radio by T. Limberg, M. Winter, M. Bimberg, M. B. S. Tavares, H. Ahlendorf, Matus G. Fettweis, H. Eisenreich, G. Ellguth, Technische Universität Dresden

155 TOMAHAWK VisoMT Reliability

156 TOMAHAWK VisoMT Reliability From SISO to MIMO

157 TOMAHAWK VisoMT Reliability Tomahawk Reference Board

158 TOMAHAWK VisoMT Reliability Block Diagram

159 TOMAHAWK VisoMT Reliability Chip Micrography

160 TOMAHAWK VisoMT Reliability Synchronous Data Flow Model by E. A. Lee, D. G. Messerschmitt, 1987 number of data samples consumed by each node specified a priori number of data samples produced by each node specified a priori nodes can be scheduled statically (at compile time)

161 TOMAHAWK VisoMT Reliability Hardware Scheduling by CoreManager simple programming no additional software for scheduling communication not interrupted based scalability

162 TOMAHAWK VisoMT Reliability How Does It Work? task descriptions created at compile-time task descriptions sent to CoreManager at run-time if all dependencies are resolved task is started memories are copied from the global to local

163 TOMAHAWK VisoMT Reliability Sequence Diagram

164 TOMAHAWK VisoMT Reliability Programming Example

165 TOMAHAWK VisoMT Reliability 2-D Memory Accesses by CoreManager and DMA Controllers

166 TOMAHAWK VisoMT Reliability Further Work on CoreManager maximize local reuse data memories hard real-time support multicore processor support power management (voltage and frequency scaling of PEs)

167 TOMAHAWK VisoMT Reliability References A Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for Software Dened Radio T. Limberg, M. Winter, M. Bimberg Technische Universität Dresden

168 TOMAHAWK VisoMT Reliability VisoMT VisoMT

169 TOMAHAWK VisoMT Reliability VisoMT Collaborative Multithreading Multicore Processor for Multimedia Applications with a Fast Data Switching Mechanism

170 TOMAHAWK VisoMT Reliability Demands audio/video electronics multimedia processing single system programable procesor based configurable architecture

171 TOMAHAWK VisoMT Reliability H.264 program segments intra-prediction macroblock (MB) references to other P-frame and B-frame may reference many frames Data exchange generally: data-exchange through local storage local storage as relay station

172 TOMAHAWK VisoMT Reliability H.264 problems

173 TOMAHAWK VisoMT Reliability Fast data switching Each core is an embedded collaborative multithreading core

174 TOMAHAWK VisoMT Reliability Fast data switching programming model

175 TOMAHAWK VisoMT Reliability Fast data switching one-stop streaming processing

176 TOMAHAWK VisoMT Reliability Fast data switching keep data circulating in the system for as long as possible

177 TOMAHAWK VisoMT Reliability Fast data switching multilevel storage

178 TOMAHAWK VisoMT Reliability Block diagram one-step streaming processor

179 TOMAHAWK VisoMT Reliability Block diagram unified L1-cache for RISC and DSP to reduce communication overhead

180 TOMAHAWK VisoMT Reliability Block diagram VisoMT RISC: master processor

181 TOMAHAWK VisoMT Reliability Block diagram DSP:4 media cores, 64-Bit SIMD path M-core

182 TOMAHAWK VisoMT Reliability Block diagram multithreading control core: T-core

183 TOMAHAWK VisoMT Reliability DSP four physical chunk threads with own flow control and data computation

184 TOMAHAWK VisoMT Reliability DSP VLIW instructions

185 TOMAHAWK VisoMT Reliability DSP thread scheduler: round robin

186 TOMAHAWK VisoMT Reliability Data access concurrent prefetches

187 TOMAHAWK VisoMT Reliability Data access poststores

188 TOMAHAWK VisoMT Reliability Data access data transpositions (ie. linear-to-square)

189 TOMAHAWK VisoMT Reliability Configurable parallel access switch two four-node ring structures

190 TOMAHAWK VisoMT Reliability Programming Design flow Step 1: The top thread creates all child threads

191 TOMAHAWK VisoMT Reliability Programming Design flow Step 2: Describes the relationships between these threads

192 TOMAHAWK VisoMT Reliability Programming Design flow Step 3: Explains how to pass the data bank in threads

193 TOMAHAWK VisoMT Reliability Programming Design flow Step 4: Prepare data and run

194 TOMAHAWK VisoMT Reliability Register bank management Split

195 TOMAHAWK VisoMT Reliability Register bank management Copy

196 TOMAHAWK VisoMT Reliability Register bank management Share

197 TOMAHAWK VisoMT Reliability Register bank management Swap

198 TOMAHAWK VisoMT Reliability Register bank management Merge

199 TOMAHAWK VisoMT Reliability Performance

200 TOMAHAWK VisoMT Reliability Performance

201 TOMAHAWK VisoMT Reliability Performance

202 TOMAHAWK VisoMT Reliability Performance

203 TOMAHAWK VisoMT Reliability VisoMT

204 TOMAHAWK VisoMT Reliability References VisoMT: a collaborative multithreading multicore processor for multimedia applications with a fast data switching mechanism Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, and Jinn-Shyan Wang IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 19, NO. 11, NOVEMBER 2009

205 TOMAHAWK VisoMT Reliability Reliability-Aware Power Management and Scheduling

206 TOMAHAWK VisoMT Reliability Temperature is the problem Trend to 3D Design High densitiy and high power results in high temperature Effective cooling on small surface is expensive High Temperature can cause the following problems open interconnect lines shorting between adjacent metal layers crack formations electromigration dialectric breakdown

207 TOMAHAWK VisoMT Reliability Low Temperature is the solution? Low Temperature means low performance Temperature cycling or large spatial temperature gradients in the die can result in stress migration package fatigue plastic deformations parametric reliability problems hot carrier injection Thermal Hotspots and large termal cycling degrade reliability, adversely affect performance and increase leakage power

208 TOMAHAWK VisoMT Reliability Failure Modelling MTTF e Ea kt k Bolzman Constant T Temperature E a Activation Energy N f = C 0 ( T ) q N f = failure after N cycles C 0 Material-dependant constant T = Temperature difference q Coffin-Manson coefficient

209 TOMAHAWK VisoMT Reliability Power Management Factors to influence on temperature dynamic frequency scaling dynamic voltage scaling adaptive body biasing clock gating (multicore) Problem: mostly a per core strategy

210 TOMAHAWK VisoMT Reliability Reliability Aware Dynamic Power Management

211 TOMAHAWK VisoMT Reliability Fast Upgrade DPM

212 TOMAHAWK VisoMT Reliability Low Temperature DPM

213 TOMAHAWK VisoMT Reliability Smooth Temperature DPM

214 TOMAHAWK VisoMT Reliability Results AF T = MTTF, AF TC = f MTTF nopm f nopm f = cycle frequency AF = Acceleration factor T T nopm Abbildung: Power Management Results

215 TOMAHAWK VisoMT Reliability Traditional Scheduler Focus on Single Processor Criteria CPU Utilization Throughput Turnaround time Waiting time Response time Goals Performance Deadline

216 TOMAHAWK VisoMT Reliability Proactive Multicore Scheduler Goals Performance Thermal Management Power Consumption Reliability and Lifetime Knowledge about chip structure View chip as a whole rather then per core Uses workload and temperature prediction

217 TOMAHAWK VisoMT Reliability Temperature and Workload Prediction Workload changes fast Serial corellation within seconds or minutes 90/10 rule User behavior Temperature prediction is easier, slow Abbildung: Temperature and workload prediction

218 TOMAHAWK VisoMT Reliability Proactive Scheduling Use temperature prediction Reallocate waiting threads Avoid stalling and migrating task Distribute temperature uniformly Minimal impact on performance Big impact on temperature Medium impact on energy consumption High impact on reliability

219 TOMAHAWK VisoMT Reliability Results Abbildung: Scheduler Comparison