Hardware Praktikum 2010

Transkript

1 HaPra Vorbesprechung Hardware Praktikum 2010 Prof. Dr. H.-J. Wunderlich Dipl.-Inf. Michael Imhof Dipl.-Inf. Stefan Holst Dipl.-Inf. Marcus Wagner

2 Agenda Organisatorisches Gesamtsystem und Synthese Programmierung LEDs Taster-Interrupts Timer Beispiel: Boot-Programm HaPra Vorbesprechung

3 Agenda Organisatorisches Gesamtsystem und Synthese Programmierung LEDs Taster-Interrupts Timer Beispiel: Boot-Programm HaPra Vorbesprechung

4 Organisatorisches Die HaPra Abschlussklausur findet in der letzten Vorlesungswoche am von 8:30 bis 9:30 Uhr in Raum V38.04 statt HaPra Vorbesprechung

5 Preis Die Gruppe eines Termins die es als erstes schafft, das Apfelmännchen mit ihrem Prozessor+Cache über die VGA-Ausgabe des FPGA-Boards fehlerfrei auszugeben bekommt eine Flasche Sekt! HaPra Vorbesprechung

6 Restliche Versuchsreihen Versuchsreihe 9 Interrupts Synthese & Laden aufs FPGA Versuchsreihe 10 Programmierung Versuchsreihe 11 Instruktionscache Versuchsreihe 12?? FPGA System Prozessor Speicher Interrupt Takt Reset Chipsatz Board-Hardware HaPra Vorbesprechung

7 Agenda Organisatorisches Gesamtsystem und Synthese Programmierung LEDs Taster-Interrupts Timer Beispiel: Boot-Programm HaPra Vorbesprechung

8 Gesamtsystem FPGA System Prozessor Speicher Interrupt Takt Reset Chipsatz Board-Hardware HaPra Vorbesprechung

9 Starten der Synthese cd ~/proc cp /cad/tools/hapra/xilinx/build.sh. Bash-Skript das alle weiteren Schritte aufruft cp /cad/tools/hapra/xilinx/system.prj. Projektdatei cp /cad/tools/hapra/xilinx/system.scr. Synthese-Skript für XST cp /cad/tools/hapra/xilinx/system.ucf. sh build.sh HaPra Vorbesprechung

10 sh build.sh rm -rf *.log *.lst *.bld *.mrp *.ng? *.ncd *.pcf system_r* *.srp *.xml xst xst -ifn system.scr ngdbuild -a -p XCV300PQ uc system.ucf system map -u system par -w system system_r bitgen -w system_r HaPra Vorbesprechung

11 xst -ifn system.scr Synthese von VHDL zu einer Netzliste system.scr: set -xsthdpini /cad/ /hapra.ini run -ifn system.prj -ifmt vhdl -top system -ofn system.ngc -ofmt NGC -p xcv300pq opt_mode Speed -opt_level 1 vhdl work alu.vhd vhdl work ctrl.vhd vhdl work pc.vhd vhdl work ir.vhd vhdl work rf.vhd vhdl work proc.vhd vhdl work system.vhd Ausgabe: system.srp (Synthese-Report) system.ngc (Netzliste) HaPra Vorbesprechung

12 system.srp Beinhaltet die Konsolen-Ausgabe von xst TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) TIMING REPORT HaPra Vorbesprechung

13 Final Report Top Level Output File Name : system.ngc Cell Usage : # LUT2 : 1104 # FDS : 147 # RAMB4_S16 : 2 Number of Slices: 2928 out of % Number of Slice Flip Flops: 2123 out of % Number of 4 input LUTs: 5602 out of % Number of IOs: 76 Number of bonded IOBs: 76 out of % Number of BRAMs: 2 out of 16 12% Number of GCLKs: 1 out of 4 25% Minimum period: ns (Maximum Frequency: MHz) Minimum input arrival time before clock: ns Maximum output required time after clock: ns Maximum combinational path delay: ns HaPra Vorbesprechung

14 system.ngc Strukturelle Netzliste mit FPGA-Primitiven Kann in VHDL uebersetzt werden: netgen -ofmt vhdl -sim system.ngc system_nl.vhd proc_inst_pc_inst_state_0 : FDCE port map ( D => Result(0), CE => proc_inst_pc_en, CLR => chipsatz_inst_reset_118_1748, C => BOARD_CLK_BUFGP_0, Q => proc_inst_pc_inst_state(0) ); proc_inst_ctrl_inst_state_out7_2 : LUT4_D generic map( INIT => X"FFFE" ) port map ( I0 => proc_inst_ctrl_inst_state_ffd4_159, I1 => proc_inst_ctrl_inst_state_ffd6_161, I2 => proc_inst_ctrl_inst_state_ffd5_160, I3 => N4457, LO => N9576, O => proc_inst_ctrl_inst_state_out71 ); chipsatz_inst_inst_mram_mem11 : RAMB4_S16 generic map( INIT_01 => X"C42C402FCFD3 085C081C085A0", INIT_02 => X"1C63446AC471 D404FC430402E", INIT_00 => X"81A ", INIT_03 => X" A8060C01E" ) port map ( CLK => BOARD_CLK_BUFGP_0, EN => BOARD_ETH_TRISTATE_OBUF_128, ADDR(5) => mem_adr(5), ADDR(4) => mem_adr(4), ADDR(3) => mem_adr(3), ADDR(2) => mem_adr(2), ADDR(1) => mem_adr(1), ADDR(0) => mem_adr(0), DO(15) => chipsatz_inst_rom_data(31), DO(14) => chipsatz_inst_rom_data(30), DO(13) => chipsatz_inst_rom_data(29), ); HaPra Vorbesprechung

15 ngdbuild -uc system.ucf system Kombiniert synthetisierte Netzliste (.ngc) mit Syntheseparametern (.ucf) Ausgaben: system.ngd (Design) system.bld (Log-Datei) netlist.lst system.ucf: INST res_power_up INIT=S; NET BOARD_RES LOC=P234; NET BOARD_BUTTON<0> LOC=P237; NET BOARD_BUTTON<1> LOC=P238; NET BOARD_BUTTON<2> LOC=P236; NET BOARD_CLK LOC=P89; NET BOARD_CLK PERIOD=40; HaPra Vorbesprechung

16 map -u system Ordnet den Zellen FPGA-Ressourcen zu Ausgabe: system.ngm (Informationen für Backannotation) system.pcf (Pinzuordnungen und -Eigenschaften) system.ncd (Gemapptes Design) system.mrp (Report) HaPra Vorbesprechung

17 par -w system system_r Platzieren und Verdrahten Platziertes und Verdrahtetes Design system_r.ncd Pinzuordnungen: system_r_pad.txt system_r_pad.csv system_r.pad Report: system_r.par (Place&Route Report) system_r.unroutes, system_r.xpi HaPra Vorbesprechung

18 system_r.par Constraint Requested Actual Logic Absolute Number of Levels Slack errors NET "BOARD_CLK_BUFGP/IBUFG" PERIOD = 40 n ns ns ns 0 s HIGH 50% All constraints were met. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 3 mins 26 secs Total CPU time to PAR completion: 3 mins 25 secs Peak Memory Usage: 189 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 0 Writing design to file system_r.ncd HaPra Vorbesprechung

19 bitgen -w system_r Überprüft das Design und wandelt es in Programmierdaten um Programmierdaten: system_r.bit Reports: system_r.drc (Design Rule Check) system_usage.xml (Statistiken im XML-Format) system_r.bgn (Log-Datei) Log muss folgende Zeile enthalten: DRC detected 0 errors and 0 warnings. HaPra Vorbesprechung

20 Kleine Fehler, Grosse Wirkung Funktioniert in ModelSim, aber nicht auf dem FPGA Demo HaPra Vorbesprechung

21 Finden der häufigsten Fehler In system.vhd exakt die vorgegebenen Port-Namen verwenden Sonst passt die UCF-Datei nicht mehr Synthese-Skripte erst anpassen, dann ausführen Speicherprotokoll eingehalten? Syntheseprotokolle und Log-Dateien auswerten Wurden Latches erzeugt? Konnten alle Constraints eingehalten werden? War der Design-Rule-Check (DRC) erfolgreich? HaPra Vorbesprechung

22 Agenda Organisatorisches Gesamtsystem und Synthese Programmierung LEDs Taster-Interrupts Timer Beispiel: Boot-Programm HaPra Vorbesprechung

23 Instruktionssatz Speicherzugriff Kontrollfluss LD ST LDIH LDIL (LDI) JMP JZ RFE NOP CALL ALU ADD SUB AND OR NOT CP SAL SAR HaPra Vorbesprechung

24 Tipps zur Programmierung Unterprogramme Explizite Programmierung eines Stacks Einheitliche Register vereinbaren: $31 Stackpointer $30 Rücksprungadresse $29 konstant 1 Lokale und globale Register Interrupthandler Lokale Register sichern, vor Beenden wiederherstellen Mit RFE beenden HaPra Vorbesprechung

25 Peripherie Heute: Timer Board-LEDs Taster Nächste Woche: Serielle Schnittstelle VGA HaPra Vorbesprechung

26 Interrupts im HaPra Taster VGA Timer I/O-Ports Ereignisse Chipsatz (Interrupt-Teil) IRQ_EN IRQ_CTRL IRQ_HDL_ADR Taster Taster Taster VGA Timer Bit IRQ IRQ_ADR IRQ_EN: Bitmaske mit zu beachtenden Interrupts HaPra-CPU Speicher- Schnittstelle IRQ_CTRL: Bitmaske mit ausgelösten Interrupts IRQ_HDL_ADR: Adresse der Unterbrechungsroutine HaPra Vorbesprechung

27 Timer Zeitmessung und Wecker IO-Port TIMER Kann beliebig geschreiben und gelesen werden Der Wert verringert sich um 1 in jeder Mikrosekunde Wenn TIMER abgelaufen ist TIMER_RELOAD TIMER hw_ctrl.asm:.def HW_CTRL_LEDS 0x def HW_CTRL_CTRL0 0x def IRQ_EN 0x def IRQ_CTRL 0x def TIMER_RELOAD 0x10400D.def TIMER 0x10400E.def IRQ_HDL_ADR 0x10400F Interrupt HaPra Vorbesprechung

28 Timer Anwendungen Zeitmessung Schreibe 0xffffffff in TIMER Lese nach einer Zeitspanne wieder aus Maximale Zeit: 72 Minuten Interrupt nach Zeitintervall Schreibe gewünschte Mikrosekunden in TIMER Erlaube Timer-Interrupt in IRQ_EN Periodische Iterrupts Setze auch TIMER_RELOAD entsprechend HaPra Vorbesprechung

29 Beispiel: Interrupts Demo HaPra Vorbesprechung

30 Board-LEDs 3 LED-Gruppen sind frei programmierbar Balkenanzeige (10 LEDs) Linke 7-Segment-Anzeige Rechte 7-Segment-Anzeige 2 IO-Ports zur Steuerung Bits 1-3 von HW_CTRL_CTRL0 aktiviert die LED-Gruppen Bits 0-23 von HW_CTRL_LEDS sprechen die 24 einzelnen LEDs an hw_ctrl.asm:.def HW_CTRL_LEDS 0x def HW_CTRL_CTRL0 0x def IRQ_EN 0x def IRQ_CTRL 0x def TIMER_RELOAD 0x10400D.def TIMER 0x10400E.def IRQ_HDL_ADR 0x10400F HaPra Vorbesprechung

31 BlinkenLEDs.org 0x80000.def time include "hw_ctrl.asm" ;period length in us ldi $0, timer ldi $1, time st $1,($0) ldi $0, timer_reload st $1,($0) ; Omitted: Setup IRQ handling, enable timer IRQ ldi $0, hw_ctrl_ctrl0 ldi $1, 0x st $1, ($0) ;enable bargraph led ldi $0, loop ldi $1, 1 loop: jmp $0 HaPra Vorbesprechung

32 BlinkenLEDs irqhdl: ldi $3, hw_ctrl_leds ld $4,($3) not $4,$4 ldi $5, 0x00ff0000 st $5,($3) and $4,$4,$5 ldi $5,0x or $4,$4,$5 st $4,($3) ldi $3, irq_ctrl ldi $4, 0x st $4,($3) rfe ;get and flip state ;first, turn all off ;mask unused bits ;turn on ;clear and leave HaPra Vorbesprechung

33 Beispiel: Taster-Interrupts.org 0x80000.include hw_ctrl.asm ldi $0, IRQ_HDL_ADR ldi $1, irqhdl st $1,($0) Taster Taster Taster VGA Timer Bit loop: jmp $1 ldi $0, IRQ_EN ldi $1, 0x f st $1, ($0) ldi $0, IRQ_CTRL ldi $1, loop ldi $28, 0x0 ldi $29, 0x1 ldi $3, 0x1c ldi $7, return irqhdl: ld $5, ($0) and $6, $5, $3 HaPra Vorbesprechung

34 Agenda Organisatorisches Gesamtsystem und Synthese Programmierung LEDs Taster-Interrupts Timer Beispiel: Boot-Programm HaPra Vorbesprechung

35 Boot-Vorgang ROM an Adresse 0x0 Lädt Daten vom Hasen in den Hauptspeicher Springt ins Hauptprogramm Status über LEDs 0x Boot-ROM jmp 0x x Hart in den Chipsatz codiert entity rom is port( rom_adr : in std_logic_vector (18 downto 0); rom_data : out std_logic_vector (31 downto 0) ); end; HAPRA- Board- Speicher 0x0BFFFF ungültig architecture behavioral of rom is begin process(rom_adr) begin 0x case rom_adr is when " " => rom_data <= " "; --LDIH $10, IO-Ports when " " => rom_data <= " "; --LDIL $10, when " " => rom_data <= " "; --LDIH $11, when " " => rom_data <= " "; --LDIL $11, when " " => rom_data <= " "; --LDIH $0, when " " => rom_data <= " "; --LDIL $0, 8 when " " => rom_data <= " "; --ST $0, ($11) when " " => rom_data HaPra 2010 <= - Vorbesprechung " "; LDIH $3, 0 35

36 Das Boot-Programm.org 0x0.def TIME def CONSOLE_WR32 0xfff80000.def CONSOLE_RD32 0xfff80001.def CONSOLE_StatusRD32 0xfff80005.def HW_CTRL_LEDS 0xfff04000.def HW_CTRL_CTRL 0xfff04001.def MEM_BASE 0x80000 ldi $10,HW_CTRL_LEDS ldi $11,HW_CTRL_CTRL ldi $0, 0x st $0, ($11) ;enable bargraph leds ldi $3, 0 ldi $5, 1 ldi $4, TIME ldi $12, adr_loop ldi $13, data_loop ldi $14, CONSOLE_RD32 ldi $15, CONSOLE_StatusRD32 ldi $16, MEM_BASE ldi $17, led_init ldi $18, cont ldi $19, wait adr_loop: call $30, $19 ld $1, ($15) jz $12, $1 ld $1,($14) jz $16, $1 ;adr available? ;load adr ;if adr=0 jump into ram data_loop: ld $2, ($15) jz $13, $2 ld $2,($14) st $2,($1) jmp $12 ;data available ;load data ;load next word wait: sub $4, $4, $5 jz $18, $4 jmp $30 cont: ldi $4, TIME ldil $3, 0 jz $17, $3 st $3, ($10) sar $3,$3 jmp $30 led_init: ldih $3, 0x80ff st $3, ($10) ldih $3, 0x0080 jmp $30 HaPra Vorbesprechung

37 Das Boot-Programm.org 0x0.def TIME def CONSOLE_WR32 0xfff80000.def CONSOLE_RD32 0xfff80001.def CONSOLE_StatusRD32 0xfff80005.def HW_CTRL_LEDS 0xfff04000.def HW_CTRL_CTRL 0xfff04001.def MEM_BASE 0x80000.org 0x0.def TIME def CONSOLE_WR32 0xfff80000.def CONSOLE_RD32 0xfff80001.def CONSOLE_StatusRD32 0xfff80005.def HW_CTRL_LEDS 0xfff04000.def HW_CTRL_CTRL 0xfff04001.def MEM_BASE 0x80000 ldi $10,HW_CTRL_LEDS ldi $11,HW_CTRL_CTRL ldi $0, 0x st $0, ($11) ldi $3, 0 ldi $5, 1 ldi $4, TIME ldi $12, adr_loop ldi $13, data_loop ldi $14, CONSOLE_RD32 ldi $15, CONSOLE_StatusRD32 ldi $16, MEM_BASE ldi $17, led_init ldi $18, cont ldi $19, wait adr_loop: call $30, $19 ld $1, ($15) jz $12, $1 ld $1,($14) jz $16, $1 ;adr available? ;enable bargraph leds ;load adr ;if adr=0 jump into ram data_loop: ld $2, ($15) jz $13, $2 ld $2,($14) st $2,($1) jmp $12 ;data available ;load data ;load next word wait: sub $4, $4, $5 jz $18, $4 jmp $30 cont: ldi $4, TIME ldil $3, 0 jz $17, $3 st $3, ($10) sar $3,$3 jmp $30 led_init: ldih $3, 0x80ff st $3, ($10) ldih $3, 0x0080 jmp $30 HaPra Vorbesprechung

38 Das Boot-Programm ldi $10,HW_CTRL_LEDS ldi $11,HW_CTRL_CTRL ldi $0, 0x ;bargraph leds st $0, ($11) ldi $3, 0 ldi $5, 1 ldi $4, TIME ldi $12, adr_loop ldi $13, data_loop ldi $14, CONSOLE_RD32 ldi $15, CONSOLE_StatusRD32 ldi $16, MEM_BASE ldi $17, led_init ldi $18, cont ldi $19, wait.org 0x0.def TIME def CONSOLE_WR32 0xfff80000.def CONSOLE_RD32 0xfff80001.def CONSOLE_StatusRD32 0xfff80005.def HW_CTRL_LEDS 0xfff04000.def HW_CTRL_CTRL 0xfff04001.def MEM_BASE 0x80000 ldi $10,HW_CTRL_LEDS ldi $11,HW_CTRL_CTRL ldi $0, 0x st $0, ($11) ldi $3, 0 ldi $5, 1 ldi $4, TIME ldi $12, adr_loop ldi $13, data_loop ldi $14, CONSOLE_RD32 ldi $15, CONSOLE_StatusRD32 ldi $16, MEM_BASE ldi $17, led_init ldi $18, cont ldi $19, wait adr_loop: call $30, $19 ld $1, ($15) jz $12, $1 ld $1,($14) jz $16, $1 data_loop: ld $2, ($15) jz $13, $2 ld $2,($14) st $2,($1) jmp $12 wait: sub $4, $4, $5 jz $18, $4 jmp $30 cont: ldi $4, TIME ldil $3, 0 jz $17, $3 st $3, ($10) sar $3,$3 jmp $30 led_init: ldih $3, 0x80ff st $3, ($10) ldih $3, 0x0080 jmp $30 ;adr available? ;enable bargraph leds ;load adr ;if adr=0 jump into ram ;data available ;load data ;load next word HaPra Vorbesprechung

39 Das Boot-Programm wait: sub $4, $4, 1 jz cont, $4 jmp $30 cont: ldi $4, TIME ldil $3, 0 jz led_init, $3 st $3, (HW_CTRL_LEDS) sar $3,$3 jmp $30 led_init: ldih $3, 0x80ff st $3, (HW_CTRL_LEDS) ldih $3, 0x0080 jmp $30 ;$4 init. with TIME ;ret. to caller.org 0x0.def TIME def CONSOLE_WR32 0xfff80000.def CONSOLE_RD32 0xfff80001.def CONSOLE_StatusRD32 0xfff80005.def HW_CTRL_LEDS 0xfff04000.def HW_CTRL_CTRL 0xfff04001.def MEM_BASE 0x80000 ldi $10,HW_CTRL_LEDS ldi $11,HW_CTRL_CTRL ldi $0, 0x st $0, ($11) ldi $3, 0 ldi $5, 1 ldi $4, TIME ldi $12, adr_loop ldi $13, data_loop ldi $14, CONSOLE_RD32 ldi $15, CONSOLE_StatusRD32 ldi $16, MEM_BASE ldi $17, led_init ldi $18, cont ldi $19, wait adr_loop: call $30, $19 ld $1, ($15) jz $12, $1 ld $1,($14) jz $16, $1 data_loop: ld $2, ($15) jz $13, $2 ld $2,($14) st $2,($1) jmp $12 wait: sub $4, $4, $5 jz $18, $4 jmp $30 cont: ldi $4, TIME ldil $3, 0 jz $17, $3 st $3, ($10) sar $3,$3 jmp $30 led_init: ldih $3, 0x80ff st $3, ($10) ldih $3, 0x0080 jmp $30 ;adr available? ;enable bargraph leds ;load adr ;if adr=0 jump into ram ;data available ;load data ;load next word HaPra Vorbesprechung

40 Das Boot-Programm adr_loop: call $30, wait ld $1, (CONSOLE_StatusRD32) ;adr? jz adr_loop, $1 ld $1,(CONSOLE_RD32) ;load adr jz MEM_BASE, $1 data_loop: ld $2, (CONSOLE_StatusRD32) ;data? jz data_loop, $2 ld $2,(CONSOLE_RD32) ;load data st $2,($1) jmp adr_loop ;load next word.org 0x0.def TIME def CONSOLE_WR32 0xfff80000.def CONSOLE_RD32 0xfff80001.def CONSOLE_StatusRD32 0xfff80005.def HW_CTRL_LEDS 0xfff04000.def HW_CTRL_CTRL 0xfff04001.def MEM_BASE 0x80000 ldi $10,HW_CTRL_LEDS ldi $11,HW_CTRL_CTRL ldi $0, 0x st $0, ($11) ldi $3, 0 ldi $5, 1 ldi $4, TIME ldi $12, adr_loop ldi $13, data_loop ldi $14, CONSOLE_RD32 ldi $15, CONSOLE_StatusRD32 ldi $16, MEM_BASE ldi $17, led_init ldi $18, cont ldi $19, wait adr_loop: call $30, $19 ld $1, ($15) jz $12, $1 ld $1,($14) jz $16, $1 data_loop: ld $2, ($15) jz $13, $2 ld $2,($14) st $2,($1) jmp $12 ;adr available? ;enable bargraph leds ;load adr ;if adr=0 jump into ram ;data available ;load data ;load next word wait: sub $4, $4, $5 jz $18, $4 jmp $30 cont: ldi $4, TIME ldil $3, 0 jz $17, $3 st $3, ($10) sar $3,$3 jmp $30 led_init: ldih $3, 0x80ff st $3, ($10) ldih $3, 0x0080 jmp $30 HaPra Vorbesprechung

41 Viel Spass im HaPra 2010!