Microcontroller Architectures and Examples Thomas Basmer telefon: 0335 5625 334 fax: 0335 5625 671 e-mail: basmer [ at ] ihp-microelectronics.com web:
Outline Microcontroller in general Introduction Main components Low-power features Architectures Von Neumann vs. Harvard RISC vs. CISC CPU in general Main components Instruction execution Microcontroller examples AVR LEON2 MSP430(X) ipms_430(x) Kapitel 1 Seite 2
Microcontroller in geneneral(1) Microcontroller µ very small control unit supervisor Kapitel 1 Seite 3
Microcontroller in general(2) Core Memory Peripherals I/O Microcontroller: Minimal processor Simple and small instruction set (< 50) Clock speed: < 20 MHz Data and address bus: 8, 16, (32) bit Normal Processor: Instruction set: 480 (x86) Clock speed: up to 3,6 GHz Data and address bus: 32, 64 bit Kapitel 1 Seite 4
Microcontroller in general(3) Core Memory Peripherals I/O Microcontroller: Timer Multiplication unit Comperator Cryptographical Components UART, SPI, I²C, ADC, DAC Normal Processor: Timer, ALU Graphical unit All you can expect ;-) Kapitel 1 Seite 5
Microcontroller in general(4) Core Memory Peripherals I/O Microcontroller: RAM: <32 kib ROM(EEPROM/FLash): <256 kib up to 1 MiB external Memory More Memory only for Data, e.g. via SPI That s it! No MMU, no virtual address space No memory/stack protection Normal Processor: Cache L1, L2, L3: <12 MiB RAM: < 4 GiB ROM: x TiB MMU, virtual address space Kapitel 1 Seite 6
Microcontroller in general(5) Core Memory Peripherals I/O Microcontroller: GPIO UART, SPI, I²C, RS323 newer one s: USB Normal Processor: USB, P/S2, LAN, PCI, Kapitel 1 Seite 7
Microcontroller in general(6) Microcontroller low-power features: Different energy modes: Idle, Active, Sleep (and some modes between) Power consumption (based on MSP430) Active mode: ~ 200 µa per MHz Idle mode: 0.7 µa Sleep mode: 0.1 µa Microcontrollers are very power efficient, because they are often used in areas where power is limited (e.g. AA batteries) Kapitel 1 Seite 8
Outline Microcontroller in general Introduction Main components Low-power features Architectures Von Neumann vs. Harvard RISC vs. CISC CPU in general Main components Instruction execution Microcontroller examples AVR LEON2 MSP430(X) ipms_430(x) Kapitel 1 Seite 9
Architectures(1) Core Von Neumann Architecture Control unit ALU Peripherals 1 memory for data and program code No memory protection The single bus is the bottleneck Same width for data and instructions Memory I/O Kapitel 1 Seite 10
Architectures(2) Core Harvard Architecture Control unit ALU Peripherals 2 separate memory Load code and data in parallel Protection of the program memory Used for DSP(Digital Signal Processor) Different width of data and instructions is possible Program Memory Data Memory I/O Kapitel 1 Seite 11
Architectures(3) v. Neumann Harvard Pro 1. Memory is flexible usable for data and code - smaller memories - Memories are the biggest part of a chip - 16kB RAM ~ 3mm² - Ipms_430x ~ 0,4 mm² - Memories are power wasting Con 1. Code and data using one bus 2. Malware can destroy or change program code 1. Faster (get instruction and data in parallel) 2. Memory protection (Malware does not affect program code) 3. Different sizes of data word and instruction word 1. If only small amount of data or code, memory space is wasted Kapitel 1 Seite 12
Architectures(4) Reduced Instruction Set Computing (RISC) no complex instructions decoding is easier fast execution 1 cyle per instruction for register to register operations several small instructions one after another fast reaction on interrupts interrupt is serviced when instruction has finished important for microcontrollers an embedded systems every instruction is hard-wired complex instructions are emulated by simple ones typical instructions: ADD, SUB, SHL, SHR, MOV, Kapitel 1 Seite 13
Architectures(5) Complex Instruction Set Computing (CISC) long instructions expensive decoding slower execution special instructions instructions are not hard-wired every instruction starts a microprogram it executes the different tasks of the instruction microprograms can be changed for optimization today pure CISC is only rare used e.g. Pentium Pro has a CISC architecture but a functional unit transfers instructions from CISC to RISC Kapitel 1 Seite 14
Architectures(6) RISC Pro 1. few instructions 2. Fast decoding and execution 3. Fast reaction on interrupts Con 1. Instructions are hard-wired optimization or correction of mistakes impossible 2. No parallel execution possible CISC 1. Complex instructions 2. Paralelism is possible 3. Changes on instruction set is possible 1. Slower decoding slower execution 2. Slow reaction on interrupts Kapitel 1 Seite 15
Outline Microcontroller in general Introduction Main components Low-power features Architectures Von Neumann vs. Harvard RISC vs. CISC CPU in general Main components Instruction execution Microcontroller examples AVR LEON2 MSP430(X) ipms_430(x) Kapitel 1 Seite 16
CPU in general(1) Decodes the instruction generates the control signals for Aritmetical Logical Unit Multiplexers and Demultiplexers Control Unit Register File Programm Counter (PC) address of the next instruction Status Register (SR) current system state Stack Pointer (SP) address of the last stack entry General Purpose Registers interim values, constants etc. Is controled by signals of the control unit Executes arithmetical logical operations like ADD, SUB, MOV, Shift left, Shift right, is fed by memory or register file ALU Kapitel 1 Seite 17
CPU in general(2) mem_o MUX MUX Control Unit ALU Register File DE MUX mem_i mab Kapitel 1 Seite 18
Stack Part of the memory CPU in general(3) Stack 0x22 It s a LIFO (Last In First Out) memory It s read and written by special operation Push, pop Contains return addresses and special data like register content Register 4 Status Register Program Counter 0x10 Current Inst. PUSH R4 SP 0x16 Kapitel 1 Seite 19
Stack Part of the memory CPU in general(4) Stack 0x22 It s a LIFO (Last In First Out) memory It s read and written by special operation Push, pop Contains return addresses and special data like register content Status Register Program Counter 0x10 Current Inst. POP R4 SP 0x14 Kapitel 1 Seite 20
CPU in general(5) At least 4 clockcycles needed to process an instruction 1. Instruction fetch 2. Instruction decode 3. Execute 4. Write back To speed up execution a pipeline is used Step: Fetch Decode Execute Write Back Program: Inst 1 Inst 1 Inst 1 Inst 1 Kapitel 1 Seite 21
CPU in general(6) Pipeline In a pipeline all 4 steps are separated into stages When one instruction passed one of the steps the next one is loaded Through-put raises with a factor of 4 Problems Non linear program flow (jumps, branches, ) Stalls in the pipeline needed Step: Fetch Decode Execute Write Back Program: Inst 4 Inst 3 Inst 2 Inst 1 Kapitel 1 Seite 22
Outline Microcontroller in general Introduction Main components Low-power features Architectures Von Neumann vs. Harvard RISC vs. CISC CPU in general Main components Instruction execution Microcontroller examples AVR LEON2 MSP430(X) ipms_430(x) Kapitel 1 Seite 23
Microcontroller examples(1) AVR 8 bit microcontroller from Atmel ATtiny(<16kB Flash), ATmega(<256kB Flash, <16kB RAM) AVR32 (32 bit DSP) RISC architecture, Harvard architecture No pipeline One instruction per cycle for register operations Instruction set: 50-135 Clock speed: <10 MHz (caused by slow memory access) Flash access: ~100 ns RAM access: ~10 ns Kapitel 1 Seite 24
Microcontroller examples(2) AVR ATtiny11/12: Power consumption at 4 MHz: Active: 2.2 ma Idle: 0.5 ma Power down: <1 µa Clock speed: <8 MHz ATmega: Power consumption at 4 MHz: Active: 1.6 ma, Power down: 0.4µA Clockspeed: <20MHz Kapitel 1 Seite 25
Microcontroller examples(3) LEON2 32 bit soft-core from Aerospace Gaisler (VHDL) Designed for space applications under contract from ESA Provided under Less GNU Public license (LGPL) and GNU Public license (GPL) Sparc V8 architecture (Scalable Processor Architecture) RISC architecture, Harvard architecture (for cache subsystem only) 5 Stage pipeline (FET,DEC,EXE,MEM,WR) Configurable register windows, MMU, interrupt controller, cache size, FPU, Kapitel 1 Seite 26
Microcontroller examples(4) Kapitel 1 Seite 27
Microcontroller examples(5) MSP430(X) 16 bit microcontroller from Texas Instruments MSP430 16 bit address bus MSP430X 20 bit address bus RISC architecture, von Neumann architecture Instruction set: 27 core instructions 24 emulated instructions Memory: < 32kB Flash, < 1kB RAM Power consumption at 4 MHz for the 5 operating modes: Active 1.2 ma LPM0: 55 µa, LPM2: 17 µa, LPM3: 0.9 µa, LPM4: 0.1 µa Kapitel 1 Seite 28
Microcontroller examples(6) Instruction width: 16 bit For MSP430X: 16 bit extension word is used Kapitel 1 Seite 29
Microcontroller examples(7) Kapitel 1 Seite 30
Microcontroller examples(8) Kapitel 1 Seite 31
Microcontroller examples(9) ACK Kapitel 1 Seite 32
Microcontroller examples(10) ipms_430(x) 16 bit microcontroller soft-core (VHDL) from Fraunhofer IPMS in Dresden ipms_430: 16 bit address bus ipms_430x: 20 bit address bus Is instruction set compatible to the MSP430(X) Same tool chain can be used Contains only the CPU and no peripherals Kapitel 1 Seite 33
References MSP430x2xx User s Guide SLAS383B (MSP430 Data Sheet) ATMEL ATtiny11 ATtiny12 Data sheet ATMEL ATmega1284P Data sheet LEON2 User s Manual Sparc Architecture Manual Version 8 ipms_430 and ipms_430(x) User s Guide www.gidf.de Kapitel 1 Seite 34
Goodby! Thank you for your attention! Kapitel 1 Seite 35