Binary adder architectures for cell-based VLSI and their synthesis
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1 Research Collection Doctoral Thesis Binary adder architectures for cell-based VLSI and their synthesis Author(s): Zimmermann, Reto Publication Date: 1997 Permanent Link: Rights / License: In Copyright - Non-Commercial Use Permitted This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library
2 Diss. ETH No Binary Adder Architectures for Cell-Based VLSI and their Synthesis A dissertation submitted to the SWISS FEDERAL INSTITUTE OF TECHNOLOGY ZURICH for the degree of Doctor of technical sciences presented by RETO ZIMMERMANN Dipl. Informatik-Ing. ETH born citizen of Vechigen BE accepted on the recommendation of Prof. Dr. W. Fichtner, examiner Prof. Dr. L. Thiele, co-examiner 1997
3 was Abstract The addition of two binary numbers is the fundamental and most often used arithmetic operation on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Therefore, bi nary adders are crucial building blocks in very large-scale integrated (VLSI) circuits. Their efficient implementation is not trivial because a costly carrypropagation operation involving all operand bits has to be performed. Many different circuit architectures for binary addition have been proposed over the last decades, covering a wide range of performance characteristics. Also, their realization at the transistor level for full-custom circuit implemen tations has been addressed intensively. However, the suitability of adder archi tectures for cell-based design and hardware synthesis both prerequisites for the ever increasing productivity in ASIC design hardly investigated. Based on the various speed-up schemes for binary addition, a compre hensive overview and a qualitative evaluation of the different existing adder architectures are given in this thesis. In addition, a new multilevel carryincrement adder architecture is proposed. It is found that the ripple-carry, the carry-lookahead, and the proposed carry-increment adders show the best overall performance characteristics for cell-based design. These three adder architectures, which together cover the entire range of possible area vs. delay trade-offs, adder architecture reported in the literature. are comprised in the more general prefix It is shown that this universal and flexible prefix adder structure also allows the realization of various customized adders and of adders fulfilling arbitrary timing and area constraints. A non-heuristic algorithm for the synthesis and optimization of prefix adders is proposed. It allows the runtime-efficient generation of area-optimal adders for given timing constraints. XI
4 beides Zusammenfassung Die Addition zweier binarer Zahlen ist die grundlegende und am meisten verwendete arithmetische Operation in Mikroprozessoren, digitalen Signalprozessoren (DSP) und datenverarbeitenden anwendungsspezifischen integrierten Schaltungen (ASIC). Deshalb stellen binare Addierer kritische Komponenten in hochintegrierten Schaltungen (VLSI) dar. Deren effiziente Realisierung ist nicht trivial, da eine teure carry-propagation Operation ausgeftihrt werden muss. Eine Vielzahl verschiedener Schaltungsarchitekturen fiir die binare Ad dition wurden in den letzten Jahrzehnten vorgeschlagen, welche sehr unterschiedliche Eigenschaften aufweisen. Zudem wurde deren Schaltungsrealisierung auf Transistorniveau bereits eingehend behandelt. Andererseits wurde die Eignung von Addiererarchitekturen fiir zellbasierte Entwicklungstechniken und fiir die automatische Schaltungssynthese Grundvoraussetzungen fiir die hohe Produktivitatssteigerung in der ASIC Entwicklung bisher kaum untersucht. Basierend auf den mannigfaltigen Beschleunigungstechniken fiir die binare Addition wird in dieser Arbeit eine umfassende Ubersicht und ein qualitativer Vergleich der verschiedenen existierenden Addiererarchitekturen gegeben. Zudem wird eine neue multilevel carry-increment Addiererarchitektur vorge schlagen. Es wird gezeigt, dass der ripple-carry, der carry-lookahead und der vorgeschlagene carry-increment Addierer die besten Eigenschaften fiir die zellbasierte Schaltungsentwicklung aufweisen. Diese drei Addiererarchitekturen, welche zusammen den gesamten Bereich moglicher Kompromisse zwischen Schaltungsflacheund VerzQgerungszeit abdecken, sind in der allgemeineren Pre/zx-Addiererarchitektur enthalten, die in der Literatur beschrieben ist. Es wird gezeigt, dass diese universelle und flexible Prefix-Addiererstruktur die Realisierung von verschiedensten spezial- XIII
5 XIV Zusammenfassung isierten Addierern mit beliebigen Zeit- und Flachenanforderungen ermoglicht. Ein nicht-heuristischer Algorithmus fiir die Synthese und die Zeitoptimierung von Prefix-Addierern wird vorgeschlagen. Dieser erlaubt die recheneffiziente Generierung flachenoptimaler Addierer unter gegebenen Anforderungen and die Verzogerungszeit.
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