Implementation of a programmable, modularly extendable cellular-neural-network signal processor
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1 Research Collection Doctoral Thesis Implementation of a programmable, modularly extendable cellular-neural-network signal processor Author(s): Lim, Drahoslav Publication Date: 1999 Permanent Link: Rights / License: In Copyright - Non-Commercial Use Permitted This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library
2 Diss. ETH No Implementationof a Programmable, ModularlyExtendable Cellular-Neural-Network Signal Processor A dissertationsubmitted to the SWISS FEDERAL INSTITUTEOF TECHNOLOGY jl-j v_j JLvJL v..-jl~jl for the degree of Doctor of TechnicalSciences presented by DRAHOSLAVLIM M.S.E.E. born June 16, 1965 Citizen of the Czech Republic accepted on the recommendationof Prof. Dr. George S. Moschytz, examiner Prof. Dr. Qiuting Huang, co-examiner 1999 %
3 Abstract A cellular neural network is a non-linear array of locally interconnected analog processors -cells which operate in parallel. In this thesis we present an architecture suitable for implementing a programmablegen eral purpose cellular neural network (CNN) processor. The architecture deals with some of the characteristics and restrictions inhererit in CMOS VLSI technologies, and allows a multi-chip, rnixed analog-digital hardware realization of a large, continuous-time CNN, with step-wise pro grammable cell interconnections,and a piece-wise linear Outputfunetion. It is a direct implementationof the network described in [1]. The input data is not inherentlyrestricted to bipolarimages. In the first Chapter we give a brief outlineof the CNN structureand its mathematicaldescriptionand examples of a few simple CNN processing tasks. Chapter 2 describes the design goals of this thesis, defines what is to be built, and translates general systemspeeifications into more detailed, cireuit-onentedspeeifications. on whosc basis we can proceed with the de sign. In Chap. 3 we present the general architecture of the blocks which form the CNN processor and the reasoning and tradeoffs involved in choosing the configurationof each block. Chapters 4 and 5 present the design of the analog and digital portions of the chip, respectively, together with relatedlayout issues. The chip was manufacttired and sampleswere available from several wafers from two different manufacturing runs. The functions and Perfor manceof the chip is verified by static measurementsandmatching results in Chap. 6. The Operation of the CNN processor chip is demonstrated in Chap. 7. Finally, in Chap. 8 we give a summary of the work done, what was achieved, and what future work could be carried out.
4 vi Abstract Keywords. cellular neural networks, artificial neural networks, programmable analog VLSI, mixed analog-digital design, master-slave tuning, auto-zero, offset nulling, image processing, 2-D signal processing, signal Classification,pattern recognition.
5 Kurzfassung Zelluläre neuronale Netzwerke (CNN) sind Anordnungen von nicht linearen, verknüpften und auf analogen Schaltungen basierten Prozes soren,welche in parallel arbeiten. Diese Arbeit befasst sich mit der Implementationeines programmier baren CNN Prozessors. Die Implementation versucht einerseits die Be sonderheiten von CMOS und VLSI Technologienauszunützen, und and rerseits ihre inherente Grenzenzu umgehen. Sie basiert auf eine modulare, analog digitalehardware Realisation von zeitstetigen CNNs mit einem diskreten Satz von wählbaren Netzwerk (' Template") Parametern, wie auch einer stückweise-linearenausgangsfunktion.die Implementati Weiterhinbrauchen on entspricht dem ursprünglichen Netzwerk von [1]. die Eingangsdaten nicht notwendigerweisebipolar zu sein. Das erste Kapitel befasst sich mit einem Überblicküber die mathe matischen Grundlagen und Gleichungen von CNNs und einigen deren Anwendungen. Kapitel 2 beschreibt die Entwurfziele und definiert den zu "bilden den" Prozessor. Es beschreibt die System- und Schaltungspezifikationen, die dann als eine Entwurfsbasis dienen. In Kapitel 3 zeigen wir die allgemeine Architektur der einzelnen Teile des CNN Prozessors mit einer Begründungder jeweiligen Konfiguratio nen und eine Beschreibungjener Engpasse, die zur Wahl dieser Konfigu rationen geführt haben. Kapitel 4 und 5 sind dem Entwurf der analogen respektive digitalen Einheiten des Prozessors gewidmet. Diese Kapitel beinhalten auch eine Beschreibungder entsprechendenlayouts. Der Prozessor wurde erfolgreich hergestellt auf mehrerewafer. Die Funktinalitätdes Prozessors wurde verifiziert mittles CNN Operationen. Zudem wurden statistische Messungenund "matching" Versuche durch geführt. Die Resultate dieser Messungen sind im Kapitel 6. Die Funk tinalität des Prozessors wird im Kapitel 7 gezeigt. vu
6 vul Kurzfassung Schliesslich, in Kapitel. 8 wir geben eine Zusammenfassungvon der Arbeit und dessen, was sie erreicht hat und was in einer zukünftigen Ar beit zu erreichen wäre, Stichworte, zelluläre neurale Netzwerke, künstlicheneurale Netzwerke, programmierbare analoge VLSI Schaltungen, gemischteanaloge/digitale Schaltungen, Abstimmung nach dem Master-Slave Prinzip, automati scher Nullabgieich, Offset-Abgleich,Bildverarbeitung, zwei-dimensionale Signalverarbeitimg,Signalklasifikation, Mustererkennune.
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